Category Physical Design

VIAs in VLSI

What are VIAs in VLSI? To connect between different metal layers, we need poly layer along with the metal layers that we are going to connect. These are basically called as VIAs. From the below picture we can see that…

Metal Layers

What are Metal Layers? To route any PG/Clock/Signal we need metal layers. Metal layers connect the points of the two ends.   There can be many numbers of metal layers which has been used to complete the routing. The number…

Routing

Overview of Routing We need the Clock Tree Synthesis database before going to the Route stage in physical design, where we have placed all the cells present in the design. Route creates physical connections to all the logical connections present…

Duty Cycle & Pulse Width

Duty Cycle The basic definition of duty cycle is on_time/(on_time+ Off_time). The on time and off time totally depends upon the rise transition and fall transition. Due to transition differences, duty cycle changes and hence the calculation becomes bad. Practically,…

Useful Skew

Useful skew is very important concept in CTS. Let’s discuss this through an example. In the above picture, we can see that the first path is having positive 15 ps of skew, second path is having negative 5 ps of…

CTS Spec File

CTS Spec File CTS spec file contains the below information: 1. Inverters or buffers to be defined which will be used to balance the clock tree. 2. CTS Exceptions (End points of clock tree). 3. Skew group information. 4. Contains…

Clock Tree Synthesis (CTS)

Clock Tree Synthesis Clock – A signal with constant rise and fall with ideally equal width (50% rise and 50% fall of the signal width) helps to control data propagation through the clock elements like Flip-Flop, Latches etc. The clock…