Talk to an engineer

Pin Placement & Power Mux Placement

Pin Placement details basically come from the TOP level design where we are having information to place pins according to the interaction with other HMs. Power mux placement is required to control sudden excessive power loss.

Swasti PujariAssociate Director, Backend Engineering
Published
Updated
Read time
1 min

Pin Placement#

  • Pin Placement details basically come from the TOP level design where we are having information to place pins according to the interaction with other HMs.
  • We need to define edge, layer and location before placing pins.
  • After pin placement, IO Pad placement happens.
  • Check pin assignment w.r.t to different design checks.

Power Mux placement#

  • Use a Power MUX (PMUX) to Switch the Retention rail.
  • Power muxes are similar to power switch which are used for the Macros present in the design.
  • We can change the offset, pitch and distance of PMUX depending upon requirement.
  • Power mux controls the read/write operation for the macros and controls sudden excessive power loss.

Written by

Swasti Pujari

Associate Director, Backend Engineering at CoreIC Technologies, with 15+ years in VLSI Physical Design and backend engineering. Previously Practice Head at UST Global, leading Physical Design, STA, EMIR, DFT, and Physical Verification. Delivered 3nm, 6nm and 7nm projects for AMD, Intel, and Microchip, and published IEEE research on hybrid AI-EDA floorplanning.

LinkedInMore about SwastiMore posts

Keep learning: Floorplan

Physical Design

CMOS Inverter: Working, VTC, Noise Margins, Delay and Power

The CMOS inverter explained for VLSI and physical design engineers: PMOS/NMOS structure and switch model, VTC regions, switching threshold, noise margins, propagation delay and slew, dynamic, short-circuit and leakage power, standard-cell layout and latch-up, its role in CTS and STA, a timing debug flowchart and interview Q&As.

Physical Design

Routing Congestion in VLSI: Causes, Analysis and Fixes

Routing congestion in VLSI explained for physical design engineers: how global routers measure GCell capacity, demand and overflow, cell density vs pin density, global, local and layer congestion, floorplan, logic and placement causes, fixes with halos, partial blockages and cell padding, the timing impact, a debugging flowchart and interview Q&As.