What is Placement Optimization?
- Optimization is the process of iterating through a design such that it meets timing, area and power specifications. The design must satisfy these multiple design objectives.
- In general, optimization can be broken down into the following areas, where timing, power and area we have already discussed and Signal Integrity we will discuss in more details during CTS and Route when route will be done:
- Signal integrity
Depending on the stages of the design, optimization can include the following operations:
– Adding buffers: If net length is too high, then we can add buffer to break the nets and get transition better which is eventually fixing timing.
– Resizing gates: Upsize and downsize of gates helps to achieve the target of timing, power, Signal Integrity and area. Sometimes this can be vice versa w.r.t to each other.
– Restructuring the Netlist: Means Gate composition or Decomposition.
– Remapping Logic: Remapping logic means changing the gates taking care of logic, that means logic is not going to be changed but gates are getting integrated or dis-integrated. EG.- Two 2 ip AND gates gives same logic what 3 ip AND gate gives.
– Swapping pins: If a high activity net is paired with high power input pin, then swap the pins and make high activity net paired with the low power input pins.
– Deleting buffer: When there are a greater number of unwanted buffers in the path and after removing few, slack is still meeting then we should delete those buffer.
– Moving Instances: Moving instances in a way that timing gets better when we move instances nearby. Eg: If a 10 micron net is there and location of these cells are at 1u, 8u and 10u, then transition may not be good between the 1u and 8u instance. So we can move the instance of 8u to 5u or 6u which will help transition better.
– Apply useful SKEW: Applying useful skew helps slack in getting divided if the slack margin is present. Timing gets better. We will discuss this topic in detail in CTS section.
– Layer optimization: Layer optimization improves the timing as layer promotion helps RC.
– Track Optimization: We optimize track based on timing optimization. As we can have tracks on lower layer that can go for more delay.
Secondary PG Routing
As we know there are many partitions now a days, so we are dealing with UPF and number of power domains. We use AON cells (we discussed in Floorplan section) in the gated partition to fulfill the power requirement. If you remember, there are two supply pins in AON (Always on Cell) where one is connected to the direct VDD and other pin need to have connection which is secondary PG supply.
Routing of the secondary power pin is called as secondary PG routing. The requirement of secondary PG supply comes when primary power is switched off. At this time, secondary power supply helps these power cells to make them on and helps switching domain. Switching domain becomes ON/OFF for certain times, so to fulfill the requirement when it is OFF, we use secondary rail supply in switching domain. Primary supply will have the voltage value defined for that power domain when it is on but secondary requirement comes when it is off and borrowed from Always on domain. We do hook-up from Always ON domain (Default Domain).
What is track optimization??
Please explain in detail
Track is where routing happens, before going to have final route, tool does a initial route and look for the best routing track which can lead to less detour for better QOR. For eg let’s take google map example where we always have more than one track to reach our destination and we always take the best one to save our time.
I hope this clarifies.
Why high activity net should be paired with low power input pin. How it helps?Can you please brief it.
High activity nets consumes more power hence to reduce the dynamic power number we optimize the high activity nets in this way.