Physical Design Flow

The physical design flow in VLSI is a critical phase in chip design, following the synthesis stage. This flow transforms the synthesized design into a physical layout, which can be fabricated on silicon. The steps in this process are intricate, involving various tools and files.

Key Inputs for Physical Implementation

To initiate physical implementation, several key inputs are required:

  • Synthesized Netlist: The output of the synthesis process, representing the design in terms of logic gates and connections.
  • Timing Library (.lib): Contains timing information for all the standard cells used in the design.
  • Library Exchange Format (LEF): Describes the physical characteristics of the cells.
  • Unified Power Format (UPF): Specifies the power intent of the design.
  • Design Exchange Format (DEF): Contains physical placement information of the components.
  • Standard Design Constraint (SDC): Lists the timing constraints for the design.

Physical Design Flow Stages


  • Involves defining the chip’s layout at a high level, including pin placement, power stripes, and ring creation.
  • Placement of physical cells like Macros, Boundary cap cell, Tap cells, Isolation cells.
  • More details on floorplanning are available in the dedicated section.


  • Focuses on arranging standard cells within the core boundary.
  • This stage addresses multiple challenges to ensure design integrity and optimizes performance.

Clock Tree Synthesis (CTS)

  • Converts the ideal clock into a real clock network within the design.
  • Key considerations include minimizing latency, balancing skew, reducing power, and ensuring proper duty cycle.


  • Involves connecting the pins of cells using metal layers, which vary across technology nodes.
  • Ensures that cells are interconnected correctly and that the design is electrically viable.

Sign-off and Verification

  • Post-routing, the design undergoes sign-off to address any remaining timing or electrical violations.
  • Engineering Change Order (ECO) processes rectify issues such as timing violations, electrical characteristics, and physical layout concerns.
  • Physical DRC/LVS cleanup ensures adherence to design rules and schematic accuracy.


  • Once the design passes DRC/LVS checks and timing analysis, it is sent for fabrication.

Tools and Techniques

  • Synthesis: DC (Synopsys), Genus (Cadence)
  • Formal Verification: LEC (Cadence)
  • Physical Design Implementation: Innovus (Cadence), ICC2 (Synopsys)
  • Timing Analysis: Prime Time (Synopsys), Tempus (Cadence)
  • DRC/LVS Analysis: ICV (Synopsys)
  • Library Characterization: Liberty (Cadence)


This article captures the essence of the physical design flow in VLSI, outlining the steps and tools involved. Each stage is crucial for ensuring the manufacturability and functionality of the final chip. My experience with various industry-standard tools and techniques has shaped this comprehensive guide, aimed at providing a clear understanding of each phase of the physical design flow.



  1. Great website and useful information. One suggestion is to have “previous”/”next” button on each page to make it easier to move between topics. That will make navigating the website easier. Please keep on adding more topics when you can. Thank you!

    • Thanks Abhijith! We’ll definitely try to implement the suggestion provided by you. We are in the process of adding new topics with unique and in depth content which are not easily available on the internet. Keep visiting the website to be updated and keep learning.

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