In physical design flow, I will introduce the overall steps in the physical design implementation. Once we are done with Synthesis we need to perform the physical implementation of the design we have from the synthesis stage. I will explain each and every corner of the steps in the physical design flow. Before that let’s understand the steps involved in physical design implementation.
From the above image we can see that to start physical implementation of the design we need to have Synthesized Netlist, Timing Library (.lib), Library Exchange Format (LEF), Unified Power Format (UPF), Design Exchange Format (DEF), Standard Design Constraint (SDC) Etc.
Once we are done importing design the very first step is to do floorplan of the design. In this stage of the physical design flow, we will deal with all the Pin Placement, Power stripes and ring creation, all physical cells placement like Macros, Boundary cap cell, Tap cells, Isolation cells etc.
To understand more about these topics theoretically and practically, you can read more at floorplan. I have explained all these in details there.
Once we are done with the floorplan we need to do placement of STD cells inside the core boundary. This stage is named as placement stage in the physical design flow.
At this stage we have lots of challenges which I will talk while explaining placement more deeply. At this stage if we have taken care of design, then at later stages we will have to face less issues.
After Placement of STD cells we need to synthesize clock tree as till now we have ideal clock propagating and we have to make them real clock.
There are many things we need to take care of at this step like Minimize Latency, Balance Skew, Power reduction, Duty Cycle and many more. I will explain all these in details in Clock Tree Synthesis.
Once we are done with Clock Tree Synthesis then we do not have cells outside the core region to be placed inside, and now it’s time to make design routable. To route the design we need different metal layers to connect pins of the cells we placed in earlier stages physically with the help of these metal layers. Metal layers vary from one technology node to another. For 90 nm and above we have 5-6 Metal layers available and now coming to 4-5 nm we have 13-14 Metal layers, which we are using to route the design.
After the route exit of the design, we need to sign-off our design which we implemented with the help of the above steps. Definitely we cannot close the timing during route exit, which means few timing violations will be left out even if your design complexity is very less, but if design complexity is very high then you must have been left out with many violations.
To get rid of these violations we need to go through the ECO stage where we work on all the remaining timing violations, Caliber violations like Clock Transition, Data Transition, Cell Output Capacitance, Logic On Clock Path, Clock Min Pulse Width, Illegal Cells (Dont Use cells), Un-clocked Registers, Dangling Nets, Weak Drivers, Bad Variation Cells (Mostly SVT to LVT) and many more which I will discuss in details in ECO section and will let you know how to fix if you have all these violations. I will try to put some scripts as well which will help you to resolve your issues with automation while doing implementations in design.
Afterwards or may be simultaneously we do work on physical DRC/LVS cleanup. Design Rule Checks (DRC) and Layout VS Schematic (LVS) rules are defined by foundry according to the foundry rules. AS chip goes for fabrication, it should not get failed by any of the rules mentioned in the DRC/LVS summary. I will discuss more about physical DRC/LVS in later pages.
Once we have cleaned DRC/LVS in the design and timing is clean we send the chip for fabrication to the foundry.
I will capture all the things I do from RTL to SignOff and the techniques which I have used for closing complex designs till now. There are many tools we require to implement these steps while going through the physical design flow. I have worked on many industry tools, so putting it here and will try to explain the uses while explaining the topics in detail.
- Synthesis – DC (Synopsys) , Genus (Cadence)
- Formal Verification – LEC (Cadence)
- Physical Design Implementation – Innovus (Cadence, Earlier named as Encounter), ICC2 (Synopsys)
- Timing – Prime Time (Synopsys), Tempus (Cadence).
- DRC/ LVS – ICV (Synopsys).
- Library Characterization – Liberty (Cadence).