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Tap Cell Placement in VLSI

Tap cells are physical only cells which are placed in the design to avoid latch-up condition and maintain VDD and VSS NWELL continuity. Let's see in details why the well tap cells are used and how the tap cell placement helps.

Swasti PujariAssociate Director, Backend Engineering
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  • Floorplan
  • Physical Design

Tap Cell Placement:#

  • Well Tap cells are physical only cells which are placed in the design to avoid latch-up condition and maintain VDD and VSS NWELL continuity.

Latch-up condition:#

Latch-up basically means a short circuit condition between power and ground. Due to this short circuit condition, a low impedance path is created. So in order to limit this resistance between power and ground connections to wells of the substrate, Tap cells are used.

  • Tap cells are technology dependent and these cells are used so that PWR and GND are connected to substrate and NWELL respectively.
  • Well tap cells should be placed before the PG grid insertion in the design based on pitch, width and offset in a column pattern.
Figure 1. Tap Cells Placement in VLSI

Written by

Swasti Pujari

Associate Director, Backend Engineering at CoreIC Technologies, with 15+ years in VLSI Physical Design and backend engineering. Previously Practice Head at UST Global, leading Physical Design, STA, EMIR, DFT, and Physical Verification. Delivered 3nm, 6nm and 7nm projects for AMD, Intel, and Microchip, and published IEEE research on hybrid AI-EDA floorplanning.

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