Category Physical Design Inputs

Physical Library (LEF)

The Physical Library or Library exchange format (LEF) is an ASCII representation of the abstract of the standard cells.  LEF file contains all the physical information of the cells (Technology and Macro cells) and nets. It also contains the Layer…

Synthesized Netlist

Also known as a gate-level netlist. It contains all the gate level information and the connection between these gates. It can be flat or hierarchical. Flat Netlist contains only one module with all the information. Hierarchical netlist contains a number…

Physical Design Inputs

Before going into all the physical design inputs in details, I want to make you understand the block level design and Full Chip Level design (FC). Mostly, partition owners are assigned with the block-level design to work on one partition…