On this page 3 sections
What are Placement and Routing Blockages in VLSI?#
There are basically two types of blockages in VLSI,.i.e., Placement Blockages and Routing Blockages. The Placement Blockages are again classified into three types. They are hard blockages, soft blockages and partial blockages. These are explained in details below.
Placement blockage
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Placement blockages are the areas where placement of cells must be avoided in the defined region. There are basically three kind of placement blockages.
Hard Blockages
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Hard blockages never allow any cells to place where the region is defined.
Soft Blockages#
Soft blockages do not allow cells to place during the placement, but this region can be used during in-place optimization, CTS, ECO etc. Basically, it is not adding any STD cell but buffers and inverters for the optimization.
Partial Blockages#
Sets a percentage of the area that is unavailable for placement.
Routing Blockage#
Routing blockages are used to prevent the route in a particular area for the specific metal layer for all nets or only signal nets or PG nets.
Halo#
- Halos are blockages which is used around the macros to prevent congestion in later stages. If we move macro, halos move with it.
- Routing Halos can prevent signal integrity issues around blocks. Adding routing halos prevent long wires from being routed within the halo region.
- The area cannot be used to place blocks or cells during placement, but can be used during in-place optimization, clock tree synthesis, ECO placement, or placement legalization (refinePlace).
Written by
Swasti Pujari
Associate Director, Backend Engineering at CoreIC Technologies, with 15+ years in VLSI Physical Design and backend engineering. Previously Practice Head at UST Global, leading Physical Design, STA, EMIR, DFT, and Physical Verification. Delivered 3nm, 6nm and 7nm projects for AMD, Intel, and Microchip, and published IEEE research on hybrid AI-EDA floorplanning.
