Placing of standard cells in the design is known as placement.
- Floating pins in netlist
- Unconstrained Pins
- Undriven Input Ports
- Unloaded Output ports
- Pin direction Mismatch
- Timing
- Check Physical constrains (mainly FP objects)
- PG grid check
- Check Legality such as orientation, overlap etc
- Check Quality Of Results (QOR)
- Global Placement
- Refine Placement (Legalization)
- Detailed Placement
- Congestion
- Performance (Timing)
- Power
- Routability
- Placement Runtime
If the number of required routing resources are more than the number of available routing tracks, then this phenomenon is known as congestion.
- Placement congestion
- Routing congestion.
- Bad Floorplan.
- High standard cell density in particular area.
- High pin density in particular area.
- Missing/Small Halos near macro cell.
- Huge number of cells sitting near the macro cell.
- Use blockages in the design, partial blockages help more in optimized way.
- Cell padding
- Module padding
- Decomposition of large cells into small cells (Pin distribution happens)
- Adding buffers
- Resizing gates
- Restructuring the Netlist
- Remapping Logic
- Swapping pins
- Deleting buffer
- Moving Instances
- Apply useful Skew
- Layer optimization
- Track Optimization
Placeopt stage does all the optimization after detail placement. Checkout the below link which says all the details about the optimization.
https://ivlsi.com/placement-optimization-vlsi-physical-design/
Cell padding is the method to reduce congestion in some particular area where there are too many cells sitting. If we use cell padding in a cell that means we basically make fool to tool and does not allow any other cells in that particular area. It is a simple tool command like “specify_cell_pad” or similar based on tools which we use in our tool.
Read Congestion from the link: https://ivlsi.com/congestion-vlsi-physical-design/
The situation where timing critical paths are getting disturbed because of placement of cells has happened too far and we don’t have timing margins on these paths, which may be because of logic groups or macros etc then we need to create a physical bound where we place these logic groups in that particular area only. Which helps us converge timing.
Global Placement
Refine placement
Detail placement
If you want to dig into these steps and wants to read more for cross questions in interview, then go for below links.
https://ivlsi.com/global-placement-vlsi-physical-design/
https://ivlsi.com/refine-placement-detailed-placement-vlsi-physical-design/
Placement objectives and quality checks are written in details in below links.
Secondary PG details are in below link.
https://ivlsi.com/placement-optimization-vlsi-physical-design/
Scan chain DEF contents and scan chain reordering are explained in below link.
https://ivlsi.com/scan-chain-reordering-vlsi-physical-design/
Partial density is basically a partial blockage, here is the link for more details.
