What are Placement and Routing Blockages in VLSI? There are basically two types of blockages in VLSI,.i.e., Placement Blockages and Routing Blockages. The Placement Blockages are again classified into three types. They are hard blockages, soft blockages and partial blockages.…
What are Floorplan Module Constraints in VLSI? There are basically five different type of module constraint. They are as follows: None A module has the attribute None, if it is not preplaced in the core design area. A module can…
Macro Placement Guidelines After Pin placement, we place macros in the design keeping in mind below rules: One thing I am sure that if you read the below points carefully, you will be able to easily place macros for any…
What are Macros? Macro Cells are the Memory cells. These IPs have been designed by some other Analog design team, which can be used in the floor plan stage of the design. Type of Macros There are following three types…
What is Floorplan? Before hitting this particular topic of Floorplan, let’s take an example of building a house. If we are going to build a house, we first specify the area for different rooms, such as balcony, kitchen, lawn, etc.…
Standard design constraints or Synopsys design constraints contains the timing and power related constraints which control design w.r.t to the spec. SDC contents: #Clock definition: To define clock, we need following four mandatory informations. 1. Clock source: it can be…
The Unified Power Format (.upf) is an IEEE standard which is used to define the power and related aspects of multi voltage design. UPF contains supply set definition, power domain definition, power switch definition, retention cell definition, level shifter cell…
The timing library (.lib) is an ASCII representation of the Timing, Power and Area associated with the standard cells. Characterization of cells under different PVT conditions results in the timing library (.lib). The delay calculation happens based on input transition…
The Physical Library or Library exchange format (LEF) is an ASCII representation of the abstract of the standard cells. LEF file contains all the physical information of the cells (Technology and Macro cells) and nets. It also contains the Layer…
The Design Exchange (DEF) file is an ASCII representation of physical information of the design. DEF contains Property definition, Die area, Row definition, Physical cell definition, STD cell definition, special net, regular nets, port, blockages, module constraints etc. Def File…