Physical Design Inputs

Before going into all the physical design inputs in details, I want to make you understand the block level design and Full Chip Level design (FC). Mostly, partition owners are assigned with the block-level design to work on one partition and then those partitions are being integrated by the FC owner, who assembles all the blocks to create entire Full chip-level design. Below are the images which explain the difference between block-level and FC level design.

Full Chip Level Design

Full Chip Design in VLSI

Block Level Design

Block Level Design in VLSI

There is one more to work on the project nowadays in the industry. The hierarchy gets divided again into SubFC level design if designs are heavy and complex to handle at the partition level.

In that case, we work on partition level to do place and route and these partitions are being assembled at SubFC level.

Now many SubFC level designs are being integrated at the FC level and then chip gets ready. Nowadays, design complexity is getting increased every year, so in order to achieve PPA (Performance, Power, Area) better, we can go for the SubFC level as well.


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