- Placement DB
- CTS Spec File
1. Inverters or buffers to be defined which will be used to balance the clock tree.
2. CTS Exceptions (End points of clock tree).
3. Skew group information.
4. Contains target Skew, max target transition and other timing constraints as per clock tree.
5. Top layer and bottom layer route info. VIA’s information which will be used during clock route.
6. Clock related info (Generated clocks {Eg. Clock divider, Clock multiplier etc}).
7. NDR Rule definition.
- Minimize Insertion Delay
- Skew Balancing
- Duty Cycle
- Pulse Width
- Clock Tree power consumption
- Signal Integrity and Crosstalk
For detailed concept visit the below link.
https://ivlsi.com/clock-tree-synthesis-cts-vlsi-physical-design/#CTS_Quality_Checks
There are many points present in the design after which we don’t need clock tree propagation. So, to avoid unnecessary buffering, we can ask the tool not to go for balancing further to these points.
There are following clock tree exceptions:
Stop Pin – No buffer/inverter insertion beyond this point (Don’t touch scenario)
Ignore Pin (Float Pins) – No DRV, No Balance
Exclude Pin – DRV Fixing but no balancing
Through Pin – DRV Fixing as well as Balancing
Please visit below link for more details.
https://ivlsi.com/clock-tree-synthesis-cts-vlsi-physical-design/
Read the below link.
https://ivlsi.com/clock-tree-synthesis-cts-vlsi-physical-design/
To understand the NDR in detail visit below link.
https://ivlsi.com/cts-spec-file-vlsi-physical-design/
For big designs like 5 mm, 8mm, or 10mm length we can not depend on the typical tool strategies to do clock tree balancing. If we will depend then there will be a very high latency number, and unnecessary buffering will happen then lots of power issues will be there and basically not acceptable clock tree. so to avoid this we create tap points in between this long size design wherever we have pipeline registers placed. In this situation we are not going to do balancing w.r.t clock port but w.r.t tap points which is also named as multi-source CTS points. Looking at these points we do clock balancing. This method we plan with local skew groups and save design from unnecessary buffering.
Clock nets are very sensitive nets. If clock is being touched and varies in ps as well then there will be huge violations. Without applying NDR on clock nets, you cant close the designs.
Stop Pin – No buffer/inverter insertion beyond this point (Don’t touch scenario)
Ignore Pin (Float Pins) – No DRV, No Balance
Exclude Pin – DRV Fixing but no balancing
Through Pin – DRV Fixing as well as Balancing
Clock buffer have equal rise time and fall time; therefore, pulse width violation is avoided.
Normal buffers may not have equal rise and fall time.
Clock buffers are usually designed such that an input signal with 50% duty cycle produces an output with 50% duty cycle.
If timing is met and still insertion delay is high, this situation leads to too much of clock tree buffering.
Hence the entire clock tree will consume more power.
To avoid this situation, we use multi point CTS balancing and creates local skew groups.
Before Clock tree synthesis, our clock propagation is ideal and clock tree has not yet been built.
Once clock tree is built, we can go for hold analysis (Skew is zero till we build CTS. We’ll discuss more in timing section).
For clock tree balancing, we need both buffer and inverter. As we know, buffer circuit is made up of even number of inverters back to back, hence by using buffer, we have more power consumption.
I will go for some skew value where clock transition will have some difference which will help lower IR Drop.
Still it will affect Power and area. Runtime increases. So we have some insertion delay target which needs to meet.
