What is Boundary Cap (End Cap) ?#
- Boundary cap cells are physical only cells. These cells are placed at the periphery of the core and power domain.
- Boundary cap cells are placed just after macro placement in the floorplan flow. These cells are placed in an array one after another.
- Boundary cap cells are placed to have N-Well tie-off. If boundary cap cells are not present in the design, then it won’t satisfy the well tie-off requirement for the core rows to prevent the foundry DRC violations.
- Boundary cap cells does not have signal connectivity. These cells connect to the power and ground rail according to the estimation of PG grid insertion.
- Boundary cap cells of different width are present in the design to manage unbreakable placement.
- Boundary cap cells are technology dependent.
- Endcap cells have dummy poly layers which help in isolating different domains and core.
In the above picture, we can see that all the boundary cap cells are sitting at the periphery of the design and within the area bounded by the boundary cap, we place Standard cells.
Written by
Swasti Pujari
Associate Director, Backend Engineering at CoreIC Technologies, with 15+ years in VLSI Physical Design and backend engineering. Previously Practice Head at UST Global, leading Physical Design, STA, EMIR, DFT, and Physical Verification. Delivered 3nm, 6nm and 7nm projects for AMD, Intel, and Microchip, and published IEEE research on hybrid AI-EDA floorplanning.
