Top 7 Latest Floorplan Interview Questions and Answers

  1. Synthesized Netlist
  2. Timing Library (LIB)
  3. Physical Library (LEF- Library Exchange Format)
  4. Design Exchange Format (DEF)
  5. Unified Power Format (UPF)
  6. Standard Design Constraint (SDC)

The timing library is an ASCII representation of the Timing, Power and Area associated with the standard cells.

  • Characterization of cells under different PVT conditions results in the timing library (.lib).
  • The delay calculation happens based on input transition (Slew) and the output capacitance (Load).
  • Nowadays, CCS and ECSM models are used to characterize the library, where the calculations are based on current models which is more accurate. (In earlier days, it was NLDM model which was based on voltage calculation.)
  • There are basically three major parts in the .lib file:
  1. Global definition
  2. Cell definition
  3. Pin definition

There are basically two types of physical libraries (LEF):

  • Tech LEF: Technology LEF file contains all the details about the Metal layer information (Type, Direction, Pitch, Offset, Area, Width, Mincut, Resistance, Capacitance, Edge Capacitance, Thickness, Antenna Model, Antenna Ratio, etc.), Via Definition (Type, Spacing, Width, Enclosure, Antenna model, Antenna Ratio etc.) , Site Info, Resistance, Capacitance, Edge Capacitance, Antenna information, etc.
  • Macro LEF: Macro/Cell LEF contains all the information about the standard cell physical information, Macro cell physical information (Class, Origin, Symmetry, Site, Pin Direction, etc.), Pin location etc.

Distance between macros = (No. of Pins * pitch *2) / Available metal Layers

Soft Blockages: Soft blockages do not allow cells to place during the placement, but this region can be used during in-place optimization, CTS, ECO etc. Basically, it is not adding any STD cell but buffers and inverters for the optimization.

Hard Blockages: Hard blockages never allow any cells to place where the region is defined.

If we place the macros at the center, then all the std cell logics will be sitting around the macros and we might get detour which will impact quality of result like timing, long nets etc. check out the macro placement guidelines in below link.



  1. Firstly, I would thank you for the articles…!!
    I have gone through your all blogs, which are very useful and helpful for gaining Knowledge.

    I have one request

    In the VLSI INTERVIEW QA blogs, when we check answers for some questions it is saying that Accordion Content. Those questions are really useful in an interview (like they are done shot questions in an interview for PD Engineer). So, could you please provide the answers to those questions which will be very helpful to prepare for an interview in a short span of time.

    Once again Thank you and Best wishes to you and your Blog…!!!

    • Thanks Anvesh..we are in a continuous process of adding more useful and unique contents to our will get many of the answers in the articles that we have posted..the answers to the questions in the QnA sections which you are asking about will be updated soon..keep visiting the website.

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