- The Physical Library or Library exchange format (LEF) is an ASCII representation of the abstract of the standard cells.
- LEF file contains all the physical information of the cells (Technology and Macro cells) and nets. It also contains the Layer definitions, VIA’s definitions, SITE definitions, Metal capacitance definitions, Macro cell definitions, macro cell dimensions, Layout of pins, Blockages informations, DRC informations given by foundry etc.
- There are basically two types of LEF:
- Tech LEF: Technology LEF file contains all the details about the Metal layer information (Type, Direction, Pitch, Offset, Area, Width, Mincut, Resistance, Capacitance, Edge Capacitance, Thickness, Antenna Model, Antenna Ratio, etc.), Via Definition (Type, Spacing, Width, Enclosure, Antenna model, Antenna Ratio etc.) , Site Info, Resistance, Capacitance, Edge Capacitance, Antenna information, etc.
- Macro LEF: Macro/Cell LEF contains all the information about the standard cell physical information, Macro cell physical information (Class, Origin, Symmetry, Site, Pin Direction, etc.), Pin location etc.
Below are the contents of LEF in details. The explanation is with ##.
VERSION 5.8; ## LEF Version
BUSBITCHARS “[]”; ## Bus bit char representation
DIVIDERCHAR “/”; ## Divide bit char representation
## Units definition for the numbers defined in this LEF. 4000*number in this case.
UNITS
DATABASE MICRON 4000;
END UNITS
##Manufacturing grid is the lowest grid, using which we calculate the elements in a design.
MANUFACTORINGGRID 0.00025;
## Site is the smallest unit of placement. We will discuss more about it in Floorplan. Below is the definition:
SITE TESTCORE
CLASS CORE
SIZE 0.068 BY 0.420;
SYMMETRY Y;
END TESTCORE
##BUFDUMMY4P is the cell name and using below syntax we define a cell in LEF:
MACRO bufdummy4p
FIXEDMASK ;
CLASS CORE ;
ORIGIN 0.0 0.0 ;
FOREIGN bufdummy4p 0.0 0.0 ;
SIZE 0.32400 BY 0.21600 ;
SYMMETRY X Y ;
SITE CCORE ;
PIN a
DIRECTION INPUT ;
USE SIGNAL ;
PORT
LAYER M1 ;
RECT 0.01600 0.07700 0.30800 0.09900 ;
END
END a
PIN vddx
DIRECTION INOUT ;
USE POWER ;
SHAPE ABUTMENT ;
PORT
LAYER M1 ;
RECT 0.00000 0.19700 0.32400 0.23500 ;
END
END vddx
PIN vssx
DIRECTION INOUT ;
USE GROUND ;
SHAPE ABUTMENT ;
PORT
LAYER M1 ;
RECT 0.00000 -0.01900 0.32400 0.01900 ;
END
END vssx
PIN z
DIRECTION OUTPUT ;
USE SIGNAL ;
PORT
LAYER M3 ;
RECT 0.05650 0.13400 0.29000 0.15400 ;
END
END z
##Below are the obstruction layers for different metal layer used to do layout of the cell buf.
OBS
LAYER M1 ;
RECT 0.01600 0.03700 0.09200 0.05900 ;
RECT 0.01600 0.11700 0.30800 0.13900 ;
LAYER M2 ;
RECT 0.06200 0.01600 0.08200 0.20000 ;
RECT 0.13400 0.01600 0.15400 0.17400 ;
LAYER M3 ;
RECT 0.03400 0.06200 0.19900 0.08200 ;
END
END bufdummy4p
