Performance (Timing)

Understanding the Performance (Timing)

Before going to understand the performance (timing), lets understand how timing is getting checked. At placement stage we have the placement of cells information, but we don’t have connection information in between the cells so how the timing analysis will be, and which layers will help complete routing.

As we know different metal layers have different metal resistance so routing can happen with any metal layer. So our assumption might go wrong.

To avoid the confusion we do route the design in a way it wont take much time as final routing takes and give a reasonable timing results w.r.t to the placement of cells we have done. This is called as trial route. Let’s understand more about the trial route.

Early Global Route (Trial Route)

  • Fast signal router needed for extraction and timing analysis
  • Useful for congestion analysis
  • Is not DRC or LVS clean. Trial Route quickly routes the design without fixing DRC or LVS violations.
  • The router is a good predictor of congestion and enables physical synthesis to use more accurate parasitic extraction information during timing optimization.
  • Running Trial Route lets you extract RCs, which you can use to determine if you are meeting your timing goals.
  • There are tool commands which gives output statistics about track usage.

We will discuss timing more in detail in Timing section. Let’s discuss the reasons, debug & analysis methods and improvement of timing at placement stage. Before going to the timing analysis let me tell you we are doing setup analysis only at placement as clock is still ideal and clock routing has not happened.

Steps to go for Timing Analysis

1. Look at the Quality Of Results (QOR) report or timing report and look for overall timing violations for all the active corners, which includes all the path groups. This will give you a broad picture about all the timing violations.

2. Now in the placement DB investigate report timing for the most violating paths. Take start and end point and highlight the path in your P&R tool GUI. Now see if the start point and end point are too far from each other, then see what’s the reason for this. If we can make the start and end point closer, then this might resolve our issue. Most of the time the reason of such violations comes due to bad floorplan.

3. Report timing from any tools gives the details about the reason. Many times you will find that few violations are still in the design which is not because the start point and end points are sitting far away, so the reason might be SDC. At this point of time, we need to investigate the SDC and correct it.

4. There are many other small reasons which creates the timing violations. We will discuss those in the Timing sections in detail. But we have to make sure that we are having a reasonable timing violation at this stage. Then only we go for placement exit.


  1. Why we will get timing violations due to sdc??
    Please explain in detail

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