Unified Power Format (.upf)

  • The Unified Power Format (.upf) is an IEEE standard which is used to define the power and related aspects of multi voltage design.
  • UPF contains supply set definition, power domain definition, power switch definition, retention cell definition, level shifter cell definition and other low power related definition.
  • UPF Content and description:

puts “Info: PIE VERSION: 2.2.18”  ##Power Intent version

##First thing we do is create power supply port for power & ground and then we define nets with the port defined.

create_supply_port vdd_ssc_cx

create_supply_net  vdd_ssc_cx -resolve parallel

connect_supply_net vdd_ssc_cx -ports vdd_ssc_cx

create_supply_port vss_dig

create_supply_net  vss_dig -resolve parallel

connect_supply_net vss_dig -ports vss_dig

## We have already defined the port and nets now we need to define the supply set with the help of these ports and nets.

create_supply_set VDD_SSC_CX_SS \

                  -function { power vdd_ssc_cx } \

                  -function { ground vss_dig } \

                  -function { nwell vdd_ssc_cx }

create_supply_port vdd_ssc_cx_int -direction out

create_supply_net  vdd_ssc_cx_int -resolve parallel

connect_supply_net vdd_ssc_cx_int -ports vdd_ssc_cx_int

create_supply_set VDD_SSC_CX_INT_SS \

                  -function { power vdd_ssc_cx_int } \

                  -function { ground vss_dig } \

                  -function { nwell vdd_ssc_cx }

##Once supply set is being defined now its time to create power domain with the elements and associated power supply set.

create_power_domain VDD_CX_INT -update \

                    -supply { primary VDD_CX_INT_SS }

##Power switch definition for the gates power domain, we will discuss deep into the power switch cells during floorplan, as of now understand the definition of power switch cells in UPF.

create_power_switch  VDD_CX_INT_gds_psw \

                     -domain               VDD_CX_INT \

                     -input_supply_port    { vdd_ext vdd_cx } \

                     -output_supply_port   { vddx    vdd_cx_int } \

                     -control_port         { enbf_in ccd_gdsc_en_few } \

                     -control_port         { enbr_in ccd_gdsc_en_rest } \

                     -on_state             { pwr_on vdd_ext { (enbf_in && enbr_in) } } \

                     -off_state            { pwr_off { !( enbf_in && enbr_in ) } }

##Retention cells definition in UPF, we will discuss more during floorplan.

set_retention CCD_RET_REG_RULE \

              -domain               VDD_CX_INT \

              -retention_supply_set VDD_CX_SS \

              -retention_condition  {ccd_gdsc_retain_ff_state}

##Isolation cell definition in UPF, we will discuss more during floorplan.

set_isolation VDD_MDM2VDDA_ISO_HIGH_TO \

              -domain               VDDA_QLINK_LV \

              -isolation_supply_set VDDA_QLINK_LV_SS \

              -clamp_value 0 \

              -elements { \                        

                                                                            test_modem/qlink_phy_reset \


##Level shifter cells definition in UPF, we will discuss more during floorplan.

set_level_shifter  VDD_VDDA2MX_LV_TO_BSCAN_SOUT \

                   -domain            VDD_MX \

                   -location          self \

                   -elements { \                               

                                                                                          test_modem/bscan_sout_serdes_vdda \



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