VLSI Course – Freshers

Physical Design – For Freshers

Start your VLSI career by joining our Physical Design course curated according to industry skill requirements and provided by industry experts.

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    Start Date

    3RD July 2021


    16 WeekENDS


    Online Classes

    Course Overview

    The physical design course is designed for fresh graduates and interns who want to avail comprehensive training to pursue a career as a physical design engineer in the VLSI industry. The course is designed keeping in mind the latest industry requirements and will be provided by trainers experienced in the field of Physical Design. During the course, all the relevant concepts, latest methods, mock interviews and guidance for entering into specific positions in the industry will be provided.

    Who can attend this Course?

    • Fresh Graduates (B.E/B.tech) in ECE/EEE/Instrumentation/Telecom.
    • Post-Graduate Freshers (M.Tech) with specializations like VLSI/Embedded/Power Electronics Communications/Instrumentation etc.
    • Experienced Faculty working in Engineering Colleges / Universities, teaching VLSI subjects having some industry (any) / teaching experience and interested to switch to the VLSI industry.


    Basic introduction on VLSI Design – 3 Hours

    Basic Digital Gates
    VLSI Design Flow
    Basics of Digital Design Flow
    Basics of Analog Design Flow
    CMOS Circuit and Charactristic
    Physical Design Flow
    Semiconductor Design Overview

    Linux Commands and their usage – 3 Hours

    Basic Linux commands
    Basics of Shell Scripting
    GVIM hacks
    Basics of TCL
    Basics of PERL
    Automation in VLSI Design

    Synthesis – 12 Hours

    Basics of Synthesis
    Synthesis Flow
    Synthesis Inputs
    Types of Synthesis
    Optimizations in Synthesis
    Timing Analysis and Debug at Synthesis Stage
    QOR analysis and debug
    DFT Overview

    Physical Design Overview and Steps – 1 Hour

    Physical Design Steps

    Physical Design Inputs – 10 Hours

    Synthesized Netlist
    Timing Library
    Physical Library
    Design Exchanged Format (DEF)
    Unified Power Format (UPF)
    Standard Design Constraint (SDC)
    Technology Files

    Floorplan – 12 Hours

    Floorplan Overview and steps
    Basics of Floorplan
    Pin Placement
    Macro definition and placement guidelines
    Physical Cells and their importance
    PG rails

    Placement – 12 Hours

    Placement Overview
    Pre-Placement Sanity Checks
    Stages of Placement
    Congestion Analysis and debug
    Timing Analysis and debug
    Placement Optimizations
    Placement Quality Checks
    Secondary PG Routing Concepts
    Timing DRC’s wrt data path

    Clock Tree Synthesis – 16 Hours

    CTS Overview
    CTS Spec Files
    Useful Skew
    CTS Steps
    CTS Quality Checks
    Integrated Clock Gating concepts
    Signal Integrity and Crosstalk
    Timing DRC’s wrt Clock Path

    Routing – 10 Hours

    Routing Overview
    Route Steps
    Route Quality Checks
    Concept of Metal layers
    VIA’s definitions and types
    DPT and TPT
    Antenna Effect
    Tiiming Analysis

    Timing – 20 Hours

    Basics of Timing Analysis
    Combinational Timing Analysis
    Sequential Timing Analysis (Setup Hold Recivery Removal)
    SPEF genreation and related concepts
    Detailed path timing Analysis
    Half Cycle and Multi Cycle Path
    Advanced level timing analysis and debug

    Scripting – 10 Hours

    Basics of TCL
    Advanced Level TCL

    Why Choose iVLSI?

    Industry Standard Courses

    The VLSI course covers a complete set of detailed course from design to tape-out.

    Expert Trainer

    One of the best trainers from the industry who has worked on many product based companies on their live projects and is presently working on the latest technologies in the industry.

    Placement Assistance

    Job assistance programs to help our learners get jobs at leading VLSI companies.

    Flexible Learning Models

    Choose a variety of learning models and courses in the most cost-effective manner as per your learning needs and budget.

    About the Instructor

    The instructor has worked with reputed product based companies like Intel, Qualcomm, Cadence, Broadcom, etc. He has 10+ years of industry experience and has worked on all the physical design, synthesis and STA tools from the industry. Besides, he has worked on various technology nodes ranging from 90nm projects to 5nm projects across TSMC, Samsung, Intel processes. In his entire career, he has worked on multiple projects such as CPU design, GPU Design, Snapdragon chips, Server chips etc.

    He has written the concepts over the iVLSI website regarding different areas and topics. Moreover, he has trained many candidates who are currently working in different organizations. According to the feedback from his students, he is a great mentor and understands students very well while helping them achieve their goals. He primarily aims at helping beginners to enter into the VLSI industry by guiding and mentoring them till they get placed.