VLSI Course – Experienced

Physical Design – For Experienced

At experience level, assuming you know the fundamentals we will brush up and focus more on advanced topics along with Design Closure strategies and more numbers of problem statements which will boost your confidence to close the designs efficiently. After completing this course, you will be able to converge any complex design till 5nm technology.

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    Start Date

    4TH July 2021


    20 WeekENDS


    Online Classes

    Course Overview

    In the last 20 years, physical design has emerged as a complex profession in VLSI and requires high level skills. The VLSI design cycle involves preparing the design to be manufactured in a specific foundry (TSMC, Global Foundries, Samsung, IBM, etc.) with a specific technology node (28nm, 16nm, 10nm, 7nm, 5nm and so on). The process involves a series of steps, including synthesis, floor plan, power plan, placement, clock tree synthesis, routing, static timing analysis, timing optimization, and finally, after completing all sign-off checks, the GDSII file is sent to the foundry. The Physical Design training for Professionals will provide you a good exposure to fully understand physical design concepts and techniques, so that you can perform your job efficiently at your respective companies and can converge complex designs easily. The physical design course is designed according to industry requirements and is provided by experts from VLSI Industry, who are presently working on the latest tools & technologies.

    Who can attend this Course?

    • Working Professionals from VLSI industry currently working in certain fields (such as RTL design, verification, FPGA design, analog layout, synthesis, STA, characterization) but want to switch to physical design (PD).
    • Working Physical Design Engineers who want to fill the gaps in their understanding and strengthen their knowledge on Physical Design efficiently to deliver in their present duties.
    • Working Professionals in Embedded / Electronics (PCB designing, assembling, testing..) and interested in changing their Career into the VLSI industry.
    • Physical Design Engineers having a career gap who want to rejoin the VLSI industry.


    Basic introduction on VLSI Design – 3 Hours

    Basic Digital Gates
    VLSI Design Flow
    Basics of Digital Design Flow
    Basics of Analog Design Flow
    CMOS Circuit and Charactristic
    Physical Design Flow
    Semiconductor Design Overview

    Linux Commands and their usage – 3 Hours

    Basic Linux commands
    Basics of Shell Scripting
    GVIM hacks
    Basics of TCL
    Basics of PERL
    Automation in VLSI Design
    Advanced Level Linux Commands and their Usage

    Synthesis – 12 Hours

    Basics of Synthesis
    Synthesis Flow
    Synthesis Inputs
    Types of Synthesis
    Optimizations in Synthesis
    Timing Analysis and Debug at Synthesis Stage
    QOR analysis and debug
    DFT Overview
    Practical exposure of Synthesis and real time Debug

    Physical Design Overview and Steps – 2 Hours

    Physical Design Steps
    Industry tool exposure for steps
    Quality check flows

    Physical Design Inputs – 10 Hours

    Synthesized Netlist
    Timing Library
    Physical Library
    Design Exchanged Format (DEF)
    Unified Power Format (UPF)
    Standard Design Constraint (SDC)
    Technology Files
    MMMC Configuration

    Floorplan – 12 Hours

    Floorplan Overview and steps
    Basics of Floorplan
    Pin Placement
    Macro definition and placement guidelines
    Physical Cells and their importance
    Physical Cells placement Guidance
    PG rails

    Placement – 12 Hours

    Placement Overview
    Pre-Placement Sanity Checks
    Placement Steps
    Congestion Analysis and debug
    Timing Analysis and debug
    Placement Optimizations
    Placement Quality Checks
    Secondary PG Routing Concepts
    Timing DRC’s wrt data path
    Cell Density and Pin density
    Global Route Congestion Analysis

    Clock Tree Synthesis – 16 Hours

    CTS Overview
    CTS Spec Files
    Useful Skew
    CTS Steps
    CTS Quality Checks
    Integrated Clock Gating concepts
    Signal Integrity and Crosstalk
    Timing DRC’s wrt Clock Path

    Routing – 10 Hours

    Routing Overview
    Route Steps
    Route Quality Checks
    Concept of Metal layers
    VIA’s definitions and types
    DPT and TPT
    Antenna Effect
    Tiiming Analysis

    Timing – 20 Hours

    Basics of Timing Analysis
    Combinational Timing Analysis
    Sequential Timing Analysis (Setup Hold Recivery Removal)
    SPEF genreation and related concepts
    Detailed path timing Analysis
    Half Cycle and Multi Cycle Path
    Advanced level timing analysis and debug
    Timing Analysis with PBA and GBA
    OCV, AOCV, POCV Timing analysis

    Scripting – 10 Hours

    Basics of TCL
    Advanced Level TCL
    Problem statements and solution
    Otimized way to write TCL
    SHELL Scripting
    AWK, SED, GREP commands usage


    Power – 3 Hours

    Power Analysis at CTS Stages
    Power Analysis at Signoff Stage
    IR Drop, EM analysis and debug

    Logical Equivalence Check – 3 Hours

    LEC Fundamentals
    LEC Analysis and Debug at Different stages of P&R

    Physical DRC – 3 Hours


    Caliber Fixes – 6 Hours

    Max Tran analysis, debug and fixes
    Max cap Analyis , debug and fixes
    Illegal cells fixes
    Low drive or high drive cells fixes
    Unlcocked Register debug Analysis and fixes
    Logic on clock path cells

    Signoff – 6 Hours

    ECO Cycles
    Generating ECO for Timing, caliber , Power etc
    Working smothly on signoff Database
    Ways to avoid the cycles in signoff stages

    Why Choose iVLSI?

    Industry Standard Courses

    The VLSI course covers a complete set of detailed course from design to tape-out.

    Expert Trainer

    One of the best trainers from the industry who has worked on many product based companies on their live projects and is presently working on the latest technologies in the industry.

    Placement Assistance

    Job assistance programs to help our learners get jobs at leading VLSI companies.

    Flexible Learning Models

    Choose a variety of learning models and courses in the most cost-effective manner as per your learning needs and budget.

    About the Instructor

    The instructor has worked with reputed product based companies like Intel, Qualcomm, Cadence, Broadcom, etc. He has 10+ years of industry experience and has worked on all the physical design, synthesis and STA tools from the industry. Besides, he has worked on various technology nodes ranging from 90nm projects to 5nm projects across TSMC, Samsung, Intel processes. In his entire career, he has worked on multiple projects such as CPU design, GPU Design, Snapdragon chips, Server chips etc.

    He has written the concepts over the iVLSI website regarding different areas and topics. Moreover, he has trained many candidates who are currently working in different organizations. According to the feedback from his students, he is a great mentor and understands students very well while helping them achieve their goals. He primarily aims at helping beginners to enter into the VLSI industry by guiding and mentoring them till they get placed.