iVLSI

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RTL Quality Effect on Synthesis

Good Quality of RTL helps synthesis converge better In this post, we are going to learn about the RTL Quality Effect on Synthesis. The quality of RTL depends on how the synthesized netlist will be, i.e., if the RTL codes are written in a good way and it has flexibility

Physical Synthesis

What is Physical Synthesis? To start physical synthesis, we need to have all the inputs like RTL, SDC, timing lib, physical lib, UPF, DEF and other tech files. At this stage, we go for initial placement and trial route after converging the logic level design into circuit level.

Types of Synthesis

Types of Synthesis There are basically two types of synthesis: 1. Logical Synthesis 2. Physical Synthesis Logical Synthesis To perform the logical synthesis, we need to have basic inputs like RTL, SDC, UPF and Timing lib. In this type of synthesis, we perform the logical level conversion to circuit level

Synthesis Overview and Inputs

What is Synthesis? Synthesis comes between the RTL Design & Verification and Physical design steps in VLSI. The meaning of synthesis is the transformation of a level of idea into another. To give an overview, let me clarify few points w.r.t flows before digging into Synthesis. RTL Design is the

VIAs in VLSI

What are VIAs in VLSI? To connect between different metal layers, we need poly layer along with the metal layers that we are going to connect. These are basically called as VIAs. From the below picture we can see that green metal is horizontal and blue is vertical, and a

Pitch, Spacing & Offset

Pitch The distance between the center to center of the metal is called as pitch. In the below picture, B is pitch. Spacing Spacing is the distance between the edge to edge metal layers. The distance A is spacing in below picture. Offset Offset is the distance between the core

Metal Layers

What are Metal Layers? To route any PG/Clock/Signal we need metal layers. Metal layers connect the points of the two ends.   There can be many numbers of metal layers which has been used to complete the routing. The number of metal layers to be used depend upon the foundry

Routing

Overview of Routing We need the Clock Tree Synthesis database before going to the Route stage in physical design, where we have placed all the cells present in the design. Route creates physical connections to all the logical connections present in the design with the help of metal layers. These

Signal Integrity and Crosstalk

What is Signal Integrity and Crosstalk? Let’s take one example. I am doing work from home in my study room attending meeting and my family is sitting in the TV room and watching some news. Even though I am sitting far, I can still hear the TV sound which is

Integrated Clock Gating (ICG) Cell & Related Concepts

Integrated Clock Gating (ICG) Cell & Related Concepts We always have target to close the design by meeting the PPA (Power, Performance, Area). Clock consumes most of the power as it has high switching activities. Being specific, clock consumes almost 20% to 40% of dynamic power. Even in the entire