Power
Power We will discuss more about power analysis in ECO section while working on PDN, for now let’s take basic glimpse of the power analysis and consumption. There are basically 2 types of power consumption in VLSI design: 1. Dynamic…
Category Floorplan
Pin Placement & Power Mux Placement
Pin Placement Pin Placement details basically come from the TOP level design where we are having information to place pins according to the interaction with other HMs. We need to define edge, layer and location before placing pins. After pin…
Power Ground Grid Insertion
Power Ground Grid Insertion The step of power-ground grid insertion is also known as stripegen. There are mainly four things we do during the stripegen step: Add Ring Add Stripe Create special route Add VIAs PG ring and stripes…
Power Switch Cell Placement in VLSI
Power Switch Cell Placement Power switch cells are physical only cells. Basically power switches are defined in UPF w.r.t power domains present in the design. We need power switch in the design to control the power depending upon the power…
Tap Cell Placement in VLSI
Tap Cell Placement: Well Tap cells are physical only cells which are placed in the design to avoid latch-up condition and maintain VDD and VSS NWELL continuity. Latch-up condition: Latch-up basically means a short circuit condition between power and ground.…
Boundary Cap Cells/End Cap Placement
What is Boundary Cap (End Cap) ? Boundary cap cells are physical only cells. These cells are placed at the periphery of the core and power domain. Boundary cap cells are placed just after macro placement in the floorplan flow.…
Level Shifter Cell
Level Shifter Cell: In most of the Low Power Designs, there are one or more power domains where we have more power domains which operates at different voltage level in a single partition. In this case, we need different…
Retention Flops
Retention Flops: These cells are special flops with multiple power supply. They are typically used as a shadow register to retain their value even if the block in which they are residing is shut down. All the paths leading…
Isolation Cell Placement
Isolation cell placement Power domains in the design has been designed in such a way that whenever it is required it gets switched on otherwise it is switched off. To control this behavior, we need isolation cells. Isolation cells…
TIE Cells in VLSI
What are TIE Cells? In the design we see that some signals are assigned to 1’b0 or 1’b1 to complete the logic requirement (assign a = 1 or 0). To make connections during physical implementation, we need to tie…