RTL design
Architecture and RTL for SoC and IP blocks.
- Architecture and micro-architecture
- RTL in SystemVerilog / Verilog
- Low-power and clocking intent
ASIC Design & Verification
Architecture to sign-off RTL.
Architecture to sign-off RTL. UVM/SystemVerilog testbenches, coverage closure, formal and gate-level sims.
What we deliver
ASIC Design & Verification
Verification
UVM environments with coverage and formal.
- UVM / SystemVerilog testbenches
- Coverage closure
- Formal and gate-level sims
IP & integration
Reusable IP and SoC integration support.
- Custom and reusable IP blocks
- SoC integration and bring-up support
- Sign-off criteria agreed up front
Semiconductor IP development previously listed separately is delivered under this practice.
RTL designUVMFormalCoverage closure
Engagement models
However you need us.
Fixed-scope project
A defined block or deliverable with a fixed price, milestones and sign-off criteria agreed up front.
Milestone engagement
Phased work for evolving specs: we commit per milestone and re-plan with you at each gate.
Dedicated engineering pod
A stable team of senior engineers, led by an iVLSI technical lead, working as an extension of yours with US-hours overlap.
Discuss this practice
Tell us the block, node and schedule. We reply within one business day.