Blog

Level shifters in VLSI explained: why low-to-high crossings need them, the cross-coupled shifter, enable level shifters, UPF set_level_shifter rules, boundary placement and secondary power, multi-voltage STA, a debug flowchart and interview Q&As.

Power gating in VLSI explained: header and footer switch cells, ring vs grid placement, rush current and daisy-chained enables, isolation, retention, the power-down/up sequence, sign-off checks, a debug flowchart and interview Q&As.

Half-cycle paths in STA explained: rise-to-fall and fall-to-rise setup and hold relations, duty-cycle and jitter modeling, where opposite-edge paths come from, worked examples, a debug flowchart and interview Q&As.

Generated clocks in STA explained: create_generated_clock options, -edges numbering, source latency through dividers, clock muxes, master-to-generated timing, a debug flowchart and interview Q&As.

Physical-only cells in VLSI explained: well taps, endcaps, fillers and decaps—roles, placement rules, illustrative examples, a debug flowchart and interview Q&As for PD sign-off.

OCV, AOCV and POCV in STA explained: flat derates, advanced tables, parametric variation, CRPR/CPPR, worked examples, a debug flowchart and interview Q&As for VLSI sign-off.