TIE Cells in VLSI Physical Design

In the design we see that some signals are assigned to 1’b0 or 1’b1 to complete the logic requirement (assign a = 1 or 0). To make connections during physical implementation, we need to tie these cells to continuous 0 or 1. If we will think then the best options we have is our power supply which is present in entire design, so physical implementation of 1’b0 or 1’b1 will be connected to VDD for 1’b1 and VSS for 1’b0. Now the problem is, if we connect these signals directly to VDD or VSS and gate oxide of the transistor, then it will get damaged continuously due to voltage fluctuation in Power/Ground. To avoid this situation, we add TIE cells in between VDD/VSS and gate oxide of the transistor.

We use Tie high cells at 1’b1 and Tie low cells at 1’b0 respectively. These cells are basically present in the .lib.

There are two types of TIE Cells:

One pin to VDD and other to signal nets

One pin to VSS and other to signal nets

TIE Cells in VLSI