Pre-Placement Sanity Checks
Before going for the placement of these standard cells, we need to have some checks known as pre-placement sanity checks as mentioned below. We perform these sanity checks at pre-placement stage of the design.
- Floating pins in netlist
- Unconstrained Pins
- Undriven Input Ports
- Unloaded Output ports
- Pin direction Mismatch
- Timing
- Check Physical constrains (mainly FP objects)
- PG grid check
- Check Legality such as orientation, overlap etc
- Check Quality Of Results (QOR)
Floating pins in netlist
In the design, there might be a case that few pins will be floating which means these pins are not connected to the elements present in design. Sometimes tool optimizes the cell of which pins are floating but the reason of floating pins can be a break in the logic done by tool or human error. So we need to check the pins which are floating before going for placement and optimization . Floating means it is just hanging in the design without any connection.
Unconstrained Pins
There might be many points in the design where number of pins has not be constrained by sdc, which means through these pins timing will not be checked. Hence we will be missing the sta analysis for these pins. There are few pins in the design which are intentionally made to be false path so that sta analysis will not happen there but this does not mean we are leaving the pins without constraining them unless it is intended.
Undriven Input Port
The ports present in the design must have a connection whether it is signal/clock/power ports. If input port is unconnected, that means the input logic we are getting through that port will not be propagated in the design, hence we will miss the logic. We need to verify this port from synthesis netlist or RTL before leaving them unconnected. Problem will arise when the intended connected logic group for these ports will not get any logic to be driven. Hence tool may optimize these logic groups which was required. Just to give you a practical example, if one key of your keyboard will not work then would you like to purchase that laptop?
Unloaded Output ports
The output port present in the design is not connected to any logics through the design, hence there will not be any output which will be propagating through this output port. So we need to check from synthesized netlist or RTL as to which is the last pin or element with which this port was connected and will fix it, otherwise the logic that was about to come through a bunch of logic group will be missed. Just imagine if the key of your keyboard works but its not resulting in your system, then you might not be purchasing this product.
Pin direction Mismatch
There are basically three types of pins present in the design – Input, output, INOUT. If one of these changes into others like inout might get converted into input or output or vice versa, then it will result into pin direction mismatch in the design. Because of this, logic propagation is impacted and we will miss the logic.
Timing
We need to check the preplacement timing once before going for placement of standard cells. If we have timing broken at this point, then definitely we need to look into the issue and correct it to have marginal/good timing. The broken timing can be because of bad floorplan or constraint issues. We need a check on these and fix it.
Check physical constraints
Checking physical constraint means we need to look into the floorplan objects, whether we have all the floorplan objects and the related constraints are properly used or not. Physical constraints mean placement blockages, routing blockages, voltage area creation, physical bounds etc. If we have proper placement and routing blockages where it was required, then we are good, and design will converge but if not then we might have more issues in further stages. I have personally faced many issues w.r.t to this. Once I had incorrect voltage area taken in due to which my placement did not converge well, and CTS was fully broken (Will discuss this more in CTS). Then I had to come back to placement and complete this step with corrected voltage area.
PG Grid Checks
We have already inserted Power/Ground in design to complete the power distribution so that all the elements present should get energy in terms of power. Many times, it happens that we might miss PG distribution in some areas. We need to check and correct this otherwise the
elements that will be sitting in these areas will not get power supply. One practical observation on missing PG grid I have seen is that tool will result into legalization issue during placement and will unnecessarily increase the runtime of the placement step.
Legality Checks
We need to check legality like orientation, overlapping etc. for the objects present in the design. If these issues are present, then we need to fix before proceeding forward.
Quality of Results
Timing groups, standard cell count, standard cell area, power information (basically leakage at this stage) will need a check as QOR gives us a short summary about the design. If there is something fishy, we need to look into what we have missed or need a check on it.
