Pre-Placement Sanity Checks
Before proceeding with the placement of standard cells, pre-placement sanity checks are performed to ensure the design is in good shape. These checks help identify potential issues early, preventing delays in the later stages of physical design. Below are the essential sanity checks that must be conducted before placement.
List of Pre-Placement Sanity Checks
- Floating Pins in Netlist
- Unconstrained Pins
- Undriven Input Ports
- Unloaded Output Ports
- Pin Direction Mismatch
- Timing Analysis
- Physical Constraints Check (FP Objects Verification)
- PG Grid Check
- Legality Checks (Orientation, Overlap, etc.)
- Quality of Results (QOR) Analysis
1. Floating Pins in Netlist
Floating pins are unconnected pins that do not link to any circuit elements. This could be due to optimization by the tool or human error. Floating pins must be checked and fixed before placement, as they indicate logic discontinuity and may affect design functionality.
📌 A floating pin is like a disconnected wire—useless unless properly connected.
2. Unconstrained Pins
Some pins in the design may not have constraints in the SDC (Synopsys Design Constraints) file, meaning timing analysis will not be performed for these pins. Although some pins are intentionally declared false paths, all pins should be explicitly constrained to ensure correctness in STA (Static Timing Analysis).
3. Undriven Input Ports
Every input port must have a valid signal connection (signal, clock, power). If an input port remains unconnected, it means the input logic will not propagate in the design, resulting in missing logic.
💡 Think of it as a disconnected keyboard key—it exists, but pressing it does nothing.
4. Unloaded Output Ports
An output port without any connected logic means no data will propagate through it, leading to a loss of functional information. Checking the synthesized netlist helps identify the last connected point and ensures that output logic is not missing.
💡 Imagine pressing a key on your keyboard but not seeing any response on the screen—this is similar to an unloaded output port.
5. Pin Direction Mismatch
In a design, pins have specific directions:
- Input
- Output
- INOUT (Bidirectional)
If a pin changes direction unexpectedly (e.g., an INOUT pin becoming INPUT or OUTPUT), logic propagation is affected, leading to missing logic and functionality errors. Pin direction mismatches must be corrected before placement.
6. Timing Analysis
Pre-placement timing analysis helps detect potential violations before standard cell placement. If timing is already broken at this stage, it could be due to:
- Bad floorplan
- Incorrect constraints
- Poor logic synthesis
Timing violations should be debugged and resolved before placement to avoid excessive iterations later.
7. Check Physical Constraints (FP Objects Verification)
Physical constraints such as:
- Placement blockages
- Routing blockages
- Voltage area definitions
- Physical boundaries
must be verified. Incorrect physical constraints can cause severe placement and CTS (Clock Tree Synthesis) issues. A common mistake is incorrect voltage area definitions, leading to placement failures and CTS breakdowns.
💡 A real-world example: Incorrect voltage area settings once caused a placement failure, completely breaking CTS. Fixing the voltage area resolved the issue.
8. PG (Power/Ground) Grid Check
Power distribution must be uniform across the design to prevent power-related failures. If certain areas lack power or ground connections, the tool may fail to legalize standard cells, leading to unnecessary placement delays.
📌 A missing PG grid can increase runtime and cause legalization failures.
9. Legality Checks (Orientation, Overlap, etc.)
Before placement, check the legality of:
- Cell orientation
- Cell overlap
- Placement density
Legalization issues must be fixed early to avoid cell misalignment or overlapping that can break the routing stage.
10. Quality of Results (QOR) Analysis
QOR (Quality of Results) provides a summary of key design metrics, including:
- Timing (setup/hold violations)
- Standard cell count and area
- Power consumption (leakage analysis)
Any suspicious QOR data should be investigated to ensure correctness before placement begins.
Final Thoughts
Pre-placement sanity checks ensure design correctness, timing integrity, and efficient placement of standard cells. Identifying issues at this stage prevents costly delays in later stages like CTS, routing, and STA.
By following these checks, we can achieve a smooth physical design flow, minimizing unnecessary iterations and ensuring a successful tape-out. 🚀