Placing of standard cells in the design is known as placement.
What are the pre placement sanity checks?
- Floating pins in netlist
- Unconstrained Pins
- Undriven Input Ports
- Unloaded Output ports
- Pin direction Mismatch
- Timing
- Check Physical constrains (mainly FP objects)
- PG grid check
- Check Legality such as orientation, overlap etc
- Check Quality Of Results (QOR)
What are the stages of placement?
- Global Placement
- Refine Placement (Legalization)
- Detailed Placement
What are the objectives/quality checks of placement?
- Congestion
- Performance (Timing)
- Power
- Routability
- Placement Runtime
If the number of required routing resources are more than the number of available routing tracks, then this phenomenon is known as congestion.
What are the types of congestion?
- Placement congestion
- Routing congestion.
What are the reasons for congestion?
- Bad Floorplan.
- High standard cell density in particular area.
- High pin density in particular area.
- Missing/Small Halos near macro cell.
- Huge number of cells sitting near the macro cell.
What are the ways to fix congestion issues?
- Use blockages in the design, partial blockages help more in optimized way.
- Cell padding
- Module padding
- Decomposition of large cells into small cells (Pin distribution happens)
What are the different ways for placement optimization?
- Adding buffers
- Resizing gates
- Restructuring the Netlist
- Remapping Logic
- Swapping pins
- Deleting buffer
- Moving Instances
- Apply useful Skew
- Layer optimization
- Track Optimization
What is there in placeopt log file? What is optimization or steps it does in this stage?
Placeopt stage does all the optimization after detail placement. Checkout the below link which says all the details about the optimization.
https://ivlsi.com/placement-optimization-vlsi-physical-design/
What are the techniques to fix timings after placement?
Please visit –https://ivlsi.com/performance-timing-vlsi-physical-design/
How does ‘specify cell padding’ work?
Cell padding is the method to reduce congestion in some particular area where there are too many cells sitting. If we use cell padding in a cell that means we basically make fool to tool and does not allow any other cells in that particular area. It is a simple tool command like “specify_cell_pad” or similar based on tools which we use in our tool.
Read Congestion from the link: https://ivlsi.com/congestion-vlsi-physical-design/
Have you use bounds/groups for placement? If yes, in what scenarios you have added those?
The situation where timing critical paths are getting disturbed because of placement of cells has happened too far and we don’t have timing margins on these paths, which may be because of logic groups or macros etc then we need to create a physical bound where we place these logic groups in that particular area only. Which helps us converge timing.
What are the steps of placement? What checks will you do in placement stage?
Global Placement
Refine placement
Detail placement
If you want to dig into these steps and wants to read more for cross questions in interview, then go for below links.
https://ivlsi.com/global-placement-vlsi-physical-design/
https://ivlsi.com/refine-placement-detailed-placement-vlsi-physical-design/
What are the checks you will perform after placement completes?
Placement objectives and quality checks are written in details in below links.
https://ivlsi.com/placement-vlsi-physical-design/
Secondary PG details are in below link.
https://ivlsi.com/placement-optimization-vlsi-physical-design/
What is scan chain reordering and why it is done during placement stage?
Scan chain DEF contents and scan chain reordering are explained in below link.
https://ivlsi.com/scan-chain-reordering-vlsi-physical-design/
How does partial density help?
Partial density is basically a partial blockage, here is the link for more details.
