Top 7 Latest Floorplan Interview Questions and Answers

What are the inputs at the floorplan stage?

1. Synthesized Netlist
2. Timing Library (LIB)
3. Physical Library (LEF- Library Exchange Format)
4. Design Exchange Format (DEF)
5. Unified Power Format (UPF)
6. Standard Design Constraint (SDC)

What are the two types of lef and what is present in both the lef ?

1. Technology LEF
2. Cell/Macro LEF

What is there in .lib file?

The timing library is an ASCII representation of the Timing, Power and Area associated with the standard cells.

• Characterization of cells under different PVT conditions results in the timing library (.lib).
• The delay calculation happens based on input transition (Slew) and the output capacitance (Load).
• Nowadays, CCS and ECSM models are used to characterize the library, where the calculations are based on current models which is more accurate. (In earlier days, it was NLDM model which was based on voltage calculation.)
• There are basically three major parts in the .lib file:

1. Global definition
2. Cell definition
3. Pin definition

What kind of physical libraries are used?

There are basically two types of physical libraries (LEF):

• Tech LEF: Technology LEF file contains all the details about the Metal layer information (Type, Direction, Pitch, Offset, Area, Width, Mincut, Resistance, Capacitance, Edge Capacitance, Thickness, Antenna Model, Antenna Ratio, etc.), Via Definition (Type, Spacing, Width, Enclosure, Antenna model, Antenna Ratio etc.) , Site Info, Resistance, Capacitance, Edge Capacitance, Antenna information, etc.
• Macro LEF: Macro/Cell LEF contains all the information about the standard cell physical information, Macro cell physical information (Class, Origin, Symmetry, Site, Pin Direction, etc.), Pin location etc.

How much space is required between macros?

Distance between macros = (No. of Pins * pitch *2) / Available metal Layers

What is the difference between soft & hard placement blockage?

Soft Blockages: Soft blockages do not allow cells to place during the placement, but this region can be used during in-place optimization, CTS, ECO etc. Basically, it is not adding any STD cell but buffers and inverters for the optimization.

Hard Blockages: Hard blockages never allow any cells to place where the region is defined.

Why is it not recommended to place the macros at the centre?

If we place the macros at the center, then all the std cell logics will be sitting around the macros and we might get detour which will impact quality of result like timing, long nets etc. check out the macro placement guidelines in below link.

https://data.ivlsi.com/macro-placement-guidelines-vlsi-physical-design/