Duty Cycle & Pulse Width

A clock that leaves the PLL with a clean 50% duty cycle almost never arrives at a flip-flop that way. Every buffer and inverter in the clock tree delays the rising edge and the falling edge by slightly different amounts, and those differences add up. By the time the clock reaches a deep sink, the high phase may be noticeably narrower than the low phase, or the other way round. If either phase becomes shorter than the minimum the flop, latch or memory needs internally, the design has a minimum pulse width (MPW) violation, and it is a hard functional failure, not just a slow path.

This guide explains where duty-cycle distortion comes from, how STA tools compute pulse-width slack (with a full worked example), how to read a pulse-width report, how MPW differs from max-transition and minimum-period checks, and a step-by-step method to fix violations after CTS. It ends with interview questions and an FAQ.

If you need a refresher on clock trees themselves, read our Clock Tree Synthesis (CTS) guide and the Static Timing Analysis overview first.

What the minimum pulse width check protects#

A sequential cell is not an ideal edge detector. Inside a master-slave flip-flop, the master latch must become transparent, capture D, and close again; the slave must do the same on the opposite phase. Each of those internal operations needs a minimum amount of time. A latch needs its enable to stay active long enough to pass data. An SRAM macro needs the clock high long enough to complete a read or write, and low long enough to precharge.

The library captures this as a pulse-width constraint on the clock pin. In Liberty it appears as min_pulse_width_high and min_pulse_width_low attributes or as a timing_type : min_pulse_width arc, sometimes dependent on the input transition. Memories usually specify it in their datasheet and timing model. Designers can also add their own requirement with SDC, for example set_min_pulse_width 0.30 [get_clocks CLK].

The check then says, for every clock pin:

• the high pulse seen at the pin must be at least the required high width, and
• the low pulse seen at the pin must be at least the required low width.

If a pulse shrinks below the requirement, the cell may not capture correctly, may go metastable, or (in the extreme case of pulse collapse) the pulse may disappear entirely somewhere inside the clock tree, so the sink never sees the edge.

Where duty-cycle distortion comes from#

Duty-cycle distortion (DCD) is the difference between the width of the high phase at the source and at the sink. It has a few common causes.

1. Unequal rise and fall delays. A CMOS stage pulls up through PMOS and pulls down through NMOS. Their drive strengths are never perfectly matched across all corners, so the rise delay and fall delay of a cell differ. A buffer is two inverters in series, and the second stage is usually much larger than the first, so a buffer's rise and fall delays can be quite asymmetric. If the rising edge through a buffer is 3 ps slower than the falling edge, the high phase shrinks by 3 ps per buffer, and the error accumulates through every buffer in the path.

2. Non-inverting chains. In a chain of buffers, every stage distorts in the same direction, so the error adds up. In a chain of inverters, the edge that is rising at one stage is falling at the next, so the rise/fall asymmetries partly cancel. This is the main reason clock trees are often built with inverters or with clock buffers designed for balanced rise and fall.

3. Slow transitions. A long wire or an overloaded driver produces a slow slew. The 50% crossing point of a slow edge is more sensitive to the receiver's switching threshold and to noise, and the rise/fall difference grows.

4. Non-clock cells in the clock path. Muxes, AND/OR gates used for clock selection, and data-path buffers accidentally used on the clock usually have worse rise/fall symmetry than dedicated clock cells. Clock gating cells are clock cells, but they still add their own asymmetry (see our clock gating and ICG post).

5. Variation and crosstalk. OCV derates and SI delta delay can push the rising edge late and the falling edge early in the same analysis, which is exactly the worst case for a high pulse.

How STA computes pulse-width slack#

For a high pulse at a clock pin, the worst case is when the rising edge arrives as late as possible and the following falling edge arrives as early as possible:

actual_high = (T_fall_source + fall_arrival_early) - (T_rise_source + rise_arrival_late) + CRPR_credit slack_high = actual_high - required_high

For a low pulse, swap the edges: the falling edge late, the next rising edge early.

Here T_rise_source and T_fall_source are the ideal edge times from the clock definition (create_clock -waveform), and the arrival terms are the propagated clock latencies for that edge. Because both edges travel through the same physical cells, applying late derates to one edge and early derates to the other over the shared path is pessimistic. Signoff tools therefore apply clock reconvergence pessimism removal (CRPR / CPPR) to pulse-width checks as well; the details depend on the tool and on whether crosstalk is considered static or dynamic. See the CRPR section of our STA guide for how the credit is computed.

Clock uncertainty, if your flow applies it to pulse-width checks, is subtracted from the actual pulse. Check your tool's documentation for which uncertainty components apply to this check.

Worked example (illustrative numbers)#

The numbers below are made up for teaching; they do not come from any real library or node.

• Clock period 1.00 ns, 50% duty cycle: rising edge at 0.00 ns, falling at 0.50 ns.
• The path to the sink has 10 clock buffers.
• At the analysis corner each buffer has rise delay 22 ps and fall delay 19 ps (nominal).
• OCV derates: late ×1.05, early ×0.95.
• Library min_pulse_width_high on the flop CK pin = 0.42 ns.

Step 1: late rising-edge arrival. 10 × 22 ps × 1.05 = 231 ps.

Step 2: early falling-edge arrival. 10 × 19 ps × 0.95 = 180.5 ps.

Step 3: actual high pulse without CRPR. (0.500 + 0.1805) − (0.000 + 0.231) = 0.4495 ns.

Step 4: CRPR credit. Both edges travel the same 10 buffers. One simple way to see it is that the derate spread on the shared path is pessimism. Removing it means using the same derate for both edges, so the effective arrivals become 220 ps (rise) and 190 ps (fall) nominal. Actual high pulse = 0.500 + 0.190 − 0.220 = 0.470 ns. CRPR credit = 0.470 − 0.4495 = 0.0205 ns. (Real tools compute this from the common-point arrival times and may not credit dynamic SI components.)

Step 5: slack. 0.470 − 0.420 = +0.050 ns (met).

Now the design closes at a higher frequency, 1.25 GHz (period 0.80 ns, falling edge at 0.40 ns), with the same tree:

• actual high = 0.400 + 0.190 − 0.220 = 0.370 ns
• slack = 0.370 − 0.420 = −0.050 ns (violated)

Two lessons come out of this. First, the distortion here is 30 ps (220 − 190) and does not change with frequency, but the pulse it is taken from does shrink. MPW violations therefore tend to appear late, when the target frequency goes up or when a deep tree is built for a high-speed clock. Second, the fix is either to make the tree more symmetric (reduce the 30 ps) or to make it shallower (fewer stages to accumulate distortion).

Suppose we replace the 10 buffers with 10 inverters of the same rise/fall delays. Edges alternate: the source rising edge sees rise, fall, rise, fall... through the chain, so it accumulates 5 × 22 + 5 × 19 = 205 ps. The source falling edge also accumulates 5 × 19 + 5 × 22 = 205 ps. The nominal distortion drops to zero, and the slack at 0.80 ns becomes 0.400 − 0.420 = −0.020 ns before derates. Still failing in this made-up case, because the requirement (0.42 ns) is larger than half the period (0.40 ns) — no tree can fix that; the clock spec or the cell choice must change. That is a real check worth doing early: if the required pulse is more than half the period at a 50% duty cycle, CTS cannot save you.

Reading a pulse-width report#

The exact format depends on the tool. The example below is representative, written in the general style of a sign-off STA report, not copied from any tool.

Pulse width check: high, clock CLK Pin: u_core/reg_a/CK (DFF_X1) Point Incr Path --------------------------------------------------------- clock CLK (rise edge) 0.000 0.000 clock network delay (propagated) 0.231 0.231 r u_core/reg_a/CK 0.231 r clock CLK (fall edge) 0.400 0.400 clock network delay (propagated) 0.181 0.581 f u_core/reg_a/CK 0.581 f clock reconvergence pessimism 0.021 0.602 --------------------------------------------------------- actual pulse width 0.371 required pulse width (high) 0.420 --------------------------------------------------------- slack (VIOLATED) -0.049

What to look at:

1. Which phase fails (high or low). This tells you which edge is the late one. A high-phase failure means rises are slower than falls along the path.
2. The two network delays. Their difference is the distortion. Expand the clock path (in PrimeTime, report_timing-style path details or report_min_pulse_width options; in Tempus, the equivalent pulse-width report with path expansion) and look at every cell's rise and fall delay. One cell with a large asymmetry is often the whole story.
3. The required value. Check where it comes from: the library cell, a memory model, or an SDC override. A copy-paste set_min_pulse_width with a too-large value is a common false alarm.
4. Whether CRPR was applied. If the pessimism line is zero on a path with a long common segment, your CRPR setting may be off for this check.

MPW vs max-transition vs minimum period#

These three checks are often confused in interviews and in reviews.

They are related: a bad transition makes distortion worse, so fixing max-transition on the clock often helps MPW too. But a clock net can pass every transition check and still fail MPW because ten individually-fine stages each shave a few picoseconds from the same phase.

A step-by-step fix method#

1. Validate the requirement. Confirm the required width and its source. If the requirement is larger than half the period, raise it with the architecture/spec owner now.
2. Identify the failing phase and the clock path. Group violations by clock and by tree branch. Many violations behind one ICG or one mux usually have one root cause.
3. Remove non-clock cells from the clock path. Replace data buffers, generic muxes and gates with their clock-cell equivalents where the library provides them. Check that dont_use and CTS cell lists really restrict CTS to clock cells.
4. Prefer inverters or symmetric clock buffers for high-speed clocks. Most CTS engines let you restrict the buffer/inverter list per clock. Rebuild the tree for the failing clock.
5. Reduce depth. Fewer stages means less accumulation. Review the floorplan: a clock root far from its sinks forces long chains. Moving the root, using a mesh or multi-tap structure for the fastest clocks, or reducing skew-balancing buffers can all reduce depth.
6. Fix slews on the clock. Tighten the clock transition target, upsize drivers, apply clock NDRs (double width/spacing, shielding) to reduce RC and crosstalk.
7. Reduce variation where it matters. Some teams use low-Vt clock cells on the most sensitive clocks to reduce delay and variation; this costs leakage, so do it selectively.
8. Re-check derates and CRPR. Make sure the derate setup for clock cells is what signoff expects and that CRPR is active for pulse-width checks.
9. Last resort: duty-cycle correction. At the system level, a PLL output or a duty-cycle corrector can supply a pre-distorted or corrected clock. This is an architecture decision, not a P&R fix.

After each change, re-run timing at all corners. MPW often fails at one corner only, where PMOS/NMOS strength is most unbalanced.

Common mistakes#

• Treating MPW as a "warning" and waiving it. It is a functional check.
• Only checking at the typical corner. Asymmetry changes with process corner and voltage.
• Fixing setup/hold first with useful skew that makes the tree deeper, then discovering MPW at signoff.
• Forgetting generated clocks: a divided clock created by a flop has its own duty cycle defined by the generated-clock definition, which must be correct.
• Ignoring memories, whose pulse-width requirements are often the strictest in the design.

Interview questions and answers#

Q1. What is a minimum pulse width violation? The high or low phase of the clock at a sequential pin is narrower than the minimum width the cell needs to operate. It is checked separately for high and low phases.

Q2. Why do clock trees cause duty-cycle distortion? Each cell has different rise and fall delays. The difference shifts the rising and falling edges by different amounts, and the shift accumulates stage by stage.

Q3. Why do inverter-based clock trees help with MPW? In an inverter chain, each edge alternates between rising and falling at successive stages, so rise/fall asymmetry tends to cancel. In a buffer chain every stage distorts in the same direction.

Q4. Which edges does STA use to compute the worst-case high pulse? Late arrival of the rising edge and early arrival of the falling edge.

Q5. Does CRPR apply to MPW checks? Yes, the two edges share the same clock path, so the shared-path pessimism is removed in signoff tools. How dynamic effects like crosstalk are credited depends on the tool.

Q6. Can increasing frequency create MPW violations without any layout change? Yes. The distortion in picoseconds stays roughly the same while the available half-period shrinks.

Q7. How is MPW different from max transition? Transition checks how slow a single edge is; MPW checks the time between two edges. A clock can pass transition checks and still fail MPW.

Q8. What is pulse collapse? An extreme case where distortion is large enough that the pulse disappears inside the clock path, so the sink never sees the edge.

FAQ#

Is MPW only a CTS problem? Mostly, because before CTS the clock is ideal and has no distortion. But clock definitions, generated clocks, IO clocks and memory requirements all play a part and should be checked earlier.

Does MPW apply to data pins? Normally the check is for clock pins (and some async pins such as reset in some libraries). Data signals are checked by setup/hold. See our setup and hold violations guide.

Why does MPW fail at one corner only? Because the balance between PMOS and NMOS strength changes with process, voltage and temperature, so the rise/fall asymmetry is corner-dependent.

Does time borrowing affect MPW on latches? Latch-based designs rely on the transparent phase, so a narrow phase both reduces the borrowing window and can violate the latch's pulse requirement. See time borrowing in VLSI.

Summary#

• MPW checks that the high and low phases at every clock pin are wide enough for the cell.
• Duty-cycle distortion comes from rise/fall asymmetry that accumulates through the clock tree, made worse by slow slews, non-clock cells, variation and crosstalk.
• Worst-case high pulse = early fall arrival − late rise arrival (+ CRPR); slack = actual − required.
• Fix with symmetric clock cells or inverters, shallower trees, better slews and correct derates — and check early that the requirement fits inside half the period.