Scan Chain Reordering in VLSI: Scan DEF, Partitions, Hold Timing and ATPG Impact

Scan insertion makes a chip testable, but it is done before placement. When the synthesis or DFT tool stitches flip-flops into scan chains, it has no idea where those flops will end up on the die, so it connects them in an order that makes sense logically, not physically. After placement, consecutive flops in a chain can sit hundreds of microns apart, and the scan wires zig-zag across the block, wasting routing tracks and adding congestion. Scan chain reordering fixes this by reconnecting the scan path in an order that follows the placement, while keeping the chains valid for test.

It touches three teams at once: physical design, DFT and test. This guide explains why reordering is needed, what the scan DEF tells the place-and-route tool, which rules the reorder engine must respect, where reordering sits in the flow, and how to debug the common problems. It includes illustrative worked examples, a debugging flowchart, interview questions and an FAQ.

Related reading: Physical Design Flow, Placement, Congestion and Design Exchange Format (DEF).

A quick refresher: what a scan chain is#

In a scan design, most flip-flops are replaced with scan flip-flops. A scan flop has a multiplexer in front of its D input with two extra pins: SI (scan in) and SE (scan enable). When SE is low, the flop captures its normal functional data. When SE is high, it captures SI instead. By connecting the Q (or a dedicated SO) output of one flop to the SI of the next, the flops form a long shift register called a scan chain.

A test shifts a pattern in with SE high, pulses the functional clock with SE low so every flop captures the logic response, then shifts the result out (while the next pattern shifts in) and compares it with expected values.

The important point for physical design: the order of flops in a chain does not matter to the logic under test. Any order works, as long as the test tools know what the order is. That freedom is what reordering uses.

Why scan chain reordering is needed#

Scan stitching happens before placement, and its order usually follows hierarchy, instance names or clock domains. The placer, on the other hand, puts flops close to the logic they talk to functionally. Keeping the original order leads to:

• Long scan nets. Each SI connection may cross a large part of the block, so the total scan wirelength can be a big fraction of the block's signal wirelength.
• Congestion. Those long nets compete for the same routing tracks as functional nets, often through the busiest regions. See Congestion for how this shows up in global routing.
• Extra buffers and DRVs. Long scan nets need buffering to meet max transition and max capacitance limits (see Design Rule Violations), which adds area and power for a path that is only used in test.
• Extra load on functional nets. If SI is driven from Q, a long scan wire loads a functional net and can slow a real timing path.

Reordering reconnects the chain so that each flop feeds a nearby flop. Total scan wirelength drops sharply, and the scan path stops fighting functional routing for tracks.

Worked example 1: wirelength before and after reordering (illustrative)#

Take one scan chain of eight flops, F1 to F8, in a 100 µm × 60 µm region. The scan-in port is at the left edge (0, 30) and the scan-out port at the right edge (100, 30). After placement, the flops land at these positions (µm):

Using Manhattan distance as a simple estimate of route length:

• Synthesis order SI → F1 → F2 → … → F8 → SO gives segment lengths 100, 105, 55, 90, 100, 60, 30, 55 and 85 µm, a total of 680 µm. The longest single hop is 105 µm.
• Placement-aware order SI → F2 → F8 → F6 → F4 → F7 → F1 → F3 → F5 → SO gives 35, 20, 25, 40, 40, 30, 50, 30 and 20 µm, a total of 290 µm. The longest hop is 50 µm.

That is about 57% less scan wire for the same eight flops, with no change to the logic under test. Real tools solve this travelling-salesman-style problem with heuristics over thousands of flops, under the constraints below. Actual savings depend on the design.

The scan DEF: what the PnR tool needs to know#

The place-and-route tool cannot reorder scan chains just by looking at the netlist, because it cannot tell which connections are scan connections that may move and which are fixed. That information comes from the DFT tool as a scan DEF, a DEF file with a SCANCHAINS section (see DEF in VLSI for the rest of the format).

For each chain, the SCANCHAINS section defines:

• START and STOP: the fixed points where the reorderable part of the chain begins and ends, either a top-level pin or a pin on a component (for example a scan compression decompressor or compactor output).
• FLOATING: a list of scan elements that may be reconnected in any order within the chain.
• ORDERED: a list of elements whose relative order must be kept. The group can move as a unit, but not be split. A typical use is a flop followed by its lockup latch, or a pre-stitched shift register.
• PARTITION (with optional MAXBITS): chains with the same partition name are compatible, so the tool may move elements between them. MAXBITS limits how long a chain may become during this repartitioning.
• BITS: how many scan bits a single component holds, used for multi-bit flops or scan segments inside a macro, so chain lengths are counted correctly.
• COMMONSCANPINS: default IN and OUT pin names, so each element does not need its pins listed.

A simplified, illustrative example:

SCANCHAINS 2 ; - chain_a1 + PARTITION CLK_A_POS MAXBITS 120 + START PIN si_a1 + FLOATING u_core/r_reg_0 ( IN SI ) ( OUT Q ) u_core/r_reg_1 ( IN SI ) ( OUT Q ) u_dp/mbff_4 ( IN SI ) ( OUT SO ) ( BITS 4 ) + ORDERED u_ctl/st_reg_3 ( IN SI ) ( OUT Q ) u_ctl/lockup_0 ( IN D ) ( OUT Q ) + STOP PIN so_a1 ; - chain_a2 + PARTITION CLK_A_POS MAXBITS 120 ... END SCANCHAINS

If the scan DEF is missing or stale, the tool either refuses to reorder or reorders against wrong information. And since the scan DEF decides everything the tool may change, PD and DFT need to agree on it early.

Rules the reorder engine must respect#

Reordering is not free-for-all. The engine has to keep every chain testable, and that brings several constraints.

1. Clock domain and clock edge. Flops on different clocks are normally kept in separate chains or separated by lockup latches, and they are put into different partitions so the tool will not mix them. Within a chain that mixes clock edges, negative-edge flops must come before positive-edge flops. If a positive-edge flop feeds a negative-edge flop during shift, the negative-edge flop captures the new value in the same cycle, the two flops behave like one bit, and data is lost on shift-out.

2. Lockup latches. A lockup latch is inserted where a chain crosses between clock domains or between regions with large clock skew, to give the scan path half a cycle of extra hold margin. The latch has to stay right after the flop it protects, which is why such pairs are listed as ORDERED in the scan DEF. For the latch behaviour itself, see Difference Between Latch and Flip-Flop.

3. Chain length balance. Test time is set by the longest chain, because every pattern needs as many shift cycles as the longest chain has bits. Inter-chain swapping must keep lengths balanced and within MAXBITS.

4. Fixed endpoints. START and STOP points do not move. With scan compression, those endpoints are the decompressor and compactor pins, so reordering happens inside each internal chain.

5. Scan segments and multi-bit cells. Pre-stitched segments inside hard macros, and multi-bit flops with an internal scan path, count as several bits and cannot be split. Banking or debanking flops after scan insertion (see Multi-Bit Flip-Flops) also changes the scan elements, so the scan DEF and the chain lengths must be kept consistent with it.

Worked example 2: why balance matters (illustrative)#

Two chains, A1 and A2, share partition CLK_A_POS with 100 flops each and MAXBITS 120. During reordering, the tool moves 10 flops from A1 to A2 because they are physically closer to A2's route, and only moves 4 back. The chains end up with 94 and 106 bits.

Every pattern now needs 106 shift cycles instead of 100. If shift time dominates test time, that is roughly 6% more tester time for every chip, for a saving of some scan wire. Most teams prefer to keep chains balanced, or within a small tolerance, and let the tool swap flops only in pairs. Check your tool's options for a balance limit and set it deliberately.

Where reordering sits in the flow#

Reordering is not a one-time step. A common sequence is:

1. Synthesis and scan insertion. The DFT tool stitches chains and writes the netlist plus the scan DEF.
2. Floorplan and pre-placement checks. The scan DEF is read with the netlist. A good pre-placement sanity check confirms that the tool traces every chain and that chain counts and lengths match the DFT reports.
3. Placement. The placer often ignores or lightly weights scan connections, so they do not pull flops away from their functional logic. Reordering then runs during or after placement optimization, using the new flop locations (see Placement Optimization).
4. Clock tree synthesis. Some flows run another reorder pass after CTS, so neighbouring flops in a chain also sit on nearby clock tree branches with small skew between them, which makes scan hold easier.
5. Routing and ECOs. The order is normally frozen after routing. Late changes go through the ECO flow.
6. Hand-off. The PnR tool writes out the final netlist and an updated scan DEF. DFT re-runs ATPG on the final netlist, and the patterns are regenerated.

Scan reordering and timing#

Scan shift normally runs at a lower frequency than the functional clock, so setup on scan paths is rarely a problem. Hold is the real issue.

A scan connection is the shortest kind of path in the design: clock-to-Q of one flop, a short wire, and the SI pin of the next flop. There is almost no logic to absorb clock skew. Reordering makes these paths even shorter, so any skew between launch and capture clocks can cause a hold violation during shift. If shift fails, every scan test fails.

Worked example 3: hold on a reordered scan path (illustrative)#

Two neighbouring flops in a reordered chain sit on different clock tree branches. At the fast corner:

• launch clock arrival = 0 ps, clock-to-Q = 45 ps, wire delay to SI = 5 ps, so data arrives at 50 ps;
• capture clock arrival = 80 ps (capture clock is late), SI hold requirement = 15 ps, so data must not change before 95 ps.

Hold slack = 50 − 95 = −45 ps. The fix choices are:

• insert a delay cell or buffer of at least 45 ps (plus margin) on the SI connection, which costs area and must be checked again at slow corners; or
• pick a neighbouring flop on the same clock branch so skew is small. With 10 ps of skew, the requirement is 25 ps and the slack becomes +25 ps with no extra cells.

This is why clock-aware reordering after CTS is valuable: it removes many scan hold violations at the source instead of fixing them with buffers. For the equations, see Setup and Hold Violations.

Also time scan paths in a dedicated scan shift mode in STA, with the shift clock and SE set correctly. If they are only timed in functional mode, real scan hold violations can stay hidden.

Verification after reordering#

Reordering changes real connectivity in the netlist, so it has to be verified:

• Chain tracing. Re-trace every chain in the PnR tool and confirm the number of chains, the number of bits in each, and that every chain still runs from its START to its STOP.
• Logic equivalence (LEC). The functional logic must be unchanged. Because the scan path is rewired, LEC is run with scan disabled (scan enable constrained inactive), so scan connections do not count as differences.
• ATPG on the final netlist. Patterns from the pre-reorder netlist are no longer valid, because the bits are in a different order. The test team must run ATPG design rule checks and regenerate patterns on the final netlist and scan DEF.
• Scan-mode STA. Check shift-mode hold and setup at all relevant corners after routing.

Debugging scan reordering problems#

Common symptoms and causes:

• The tool reports no reordering, or very little. The scan DEF was not read, its names do not match the netlist (for example after renaming or ungrouping), or every element is ORDERED.
• Chain tracing fails. A chain is broken by a netlist change after scan insertion, such as a banked multi-bit flop, a removed flop, or a buffer the tool does not see through.
• Chain lengths drift. Partitions are too wide or no balance limit is set.
• ATPG DRC fails after hand-off. Edge ordering or lockup latches were broken, or the test team used a stale scan DEF.
• Many scan hold violations. Reordering ignored the clock tree. Reorder again after CTS with clock awareness, then fix the remaining ones with hold buffers.

Interview questions and answers#

1. What is scan chain reordering? It is reconnecting the order of flip-flops in scan chains after placement so that each flop feeds a nearby flop. It reduces scan wirelength and congestion without changing the logic under test.

2. Why is it needed if the DFT tool already built the chains? Scan insertion happens before placement, so the stitching order does not match where the flops are placed. Keeping the original order leads to long scan nets, wasted routing tracks and extra buffers.

3. What is a scan DEF? A DEF file with a SCANCHAINS section that tells the PnR tool, for each chain, its START and STOP points, which elements are FLOATING (reorderable), which are ORDERED (fixed order), and which chains share a PARTITION.

4. What does PARTITION mean in a scan DEF? Chains with the same partition name are compatible, so the tool may move flops between them. MAXBITS limits how long any chain in the partition may become.

5. Why must negative-edge flops come before positive-edge flops in a mixed chain? If a positive-edge flop feeds a negative-edge flop, the negative-edge flop captures the new value half a cycle later in the same shift cycle, so both hold the same bit and one bit is lost.

6. What is a lockup latch and how does reordering treat it? It is a latch inserted between flops on different clocks or with large skew, to add hold margin on the scan path. It must stay directly after its flop, so the pair is kept as an ORDERED segment.

7. Why are scan paths prone to hold violations after reordering? They are very short paths with no logic, so even moderate clock skew between neighbouring flops can make data arrive before the capture flop's hold window closes.

8. Do you need to rerun ATPG after reordering? Yes. The bit order of each chain has changed, so patterns from the old netlist are no longer valid. ATPG is run again on the final netlist and scan DEF.

9. Why should chains stay balanced? Shift cycles per pattern equal the length of the longest chain, so an unbalanced chain increases test time for every chip.

FAQ#

When is scan chain reordering done? Mainly after placement, and in many flows again after clock tree synthesis. The order is usually frozen after routing.

What happens with scan compression? Each internal chain runs between fixed decompressor and compactor pins, so reordering is done inside each internal chain within those endpoints.

Is scan reordering a DFT task or a PD task? Both. The PnR tool performs it, but DFT defines what is allowed through the scan DEF and must regenerate patterns afterwards.

Summary#

• Scan chain order from synthesis ignores placement, which causes long scan wires, congestion and extra buffers.
• Reordering reconnects each chain in placement order, without changing the logic under test.
• The scan DEF defines START/STOP, FLOATING and ORDERED elements, partitions and MAXBITS, and so controls what the tool may change.
• Respect clock domains, edge ordering, lockup latches, chain balance and multi-bit or segment bit counts.
• Scan shift paths are hold-critical; clock-aware reordering after CTS reduces hold fixes.
• After reordering, re-trace chains, run LEC with scan disabled, check scan-mode STA, and regenerate ATPG patterns from the final netlist and scan DEF.

References#

• Cadence Design Systems, LEF/DEF Language Reference (version 5.8), SCANCHAINS section.
• M. L. Bushnell and V. D. Agrawal, Essentials of Electronic Testing for Digital, Memory and Mixed-Signal VLSI Circuits, Springer, 2000.
• L.-T. Wang, C.-W. Wu and X. Wen (eds.), VLSI Test Principles and Architectures: Design for Testability, Morgan Kaufmann, 2006.