Retention Flops:
- These cells are special flops with multiple power supply. They are typically used as a shadow register to retain their value even if the block in which they are residing is shut down. All the paths leading to these registers need to be ‘always on’ and hence special care must be taken to synthesize/place/route them.
- The retention flop has the same structure as a standard master-slave flop. However, the retention flop has a balloon latch that is connected to true-Vdd. With the proper series of control signals before sleep, the data in the flop can be written into the balloon latch. Similarly, when the block comes out of sleep, the data can be written back into the flip-flop.
- Retention registers are special low leakage flip-flops used to hold the data of the main registers of the power gated block. Thus, the internal state of the block during power down mode can be retained and loaded back to it when the block is reactivated. The retention strategy is design dependent. A power gating controller controls the retention mechanism like when to save the current contents of the power gating block and when to restore it back.
