Backside Power Delivery (BSPDN): How It Changes the Physical Design Flow

For as long as most physical designers have worked, power and signals have shared the same metal stack on the front of the wafer. Thick top metals carry power down from the bumps, through a ladder of vias, to the thin rails in the standard-cell rows, and every strap and via that power uses is a track that signals cannot. Backside power delivery (BSPDN) breaks that rule: the wafer is thinned, and power is delivered from the back of the die, directly to the device layer, through nano-scale vias or backside contacts. The front-side metal stack is left mostly for signals.

This is no longer a research idea. Intel ships backside power as PowerVia on its 18A node, and TSMC has announced Super Power Rail for its A16 node. Most articles about it explain the process. This one is for physical designers: what actually changes in floorplanning, the power grid, placement, CTS, routing, IR/EM and thermal signoff, and what you should ask your foundry and EDA vendor before you start a block.

Everything below is based on public material only (vendor announcements, imec and conference papers, linked at the end). Foundry-specific rules are under NDA and will differ; treat all numbers marked illustrative as teaching numbers.

Frontside vs backside power, in one picture#

In a frontside PDN:

• power enters through bumps on the top, travels down the thick top metals, and then through every intermediate layer to the cell rails;
• straps on intermediate layers block signal tracks and create pin-access problems near the rails;
• the long via path down the stack adds resistance, and that resistance is a large part of the IR drop at advanced nodes.

In a backside PDN:

• the wafer is bonded to a carrier and thinned from the back until the device layer is reachable;
• backside metal layers, usually coarse and low-resistance, form the power grid;
• nano-TSVs or direct backside contacts connect that grid to the cells (imec describes buried power rails reached by nTSVs; Intel describes nano-TSVs in every standard cell; TSMC describes a backside contact to the source/drain);
• power bumps move to the back of the die.

The front side keeps its signal layers, and many of the tracks that power used to consume are now free.

What the vendors and researchers report#

Only use numbers you can trace. These are the public claims, each from its own source:

• Intel describes PowerVia as relocating coarse-pitch metals and bumps to the back of the die with nano-TSVs embedded in standard cells, and in its 18A technology brief reports, for routed logic designs, roughly a 10× reduction in worst-case dynamic voltage droop, 8–10% routing-closure improvement, and 6–11% block-level compaction depending on power-grid assumptions (Intel 18A; Intel newsroom).
• TSMC announced in April 2024 that A16 combines nanosheet transistors with Super Power Rail, and stated 8–10% speed improvement at the same Vdd, 15–20% power reduction at the same speed and up to 1.10× chip density versus N2P, for data-center products (TSMC press release).
• imec describes the BPR + nTSV approach and lists the expected benefits as lower IR drop, relieved BEOL routing, and potential further cell-height scaling (imec).

These are vendor-reported figures on their own designs. Your block will differ.

Impact on each stage of the PD flow#

1. Floorplanning#

• Power planning moves to a different layer set. Your PDN script now describes backside layers, backside vias and the connection to the cells, not M-something straps. Expect new technology-file constructs and new commands for backside objects in your P&R tool.
• Macro placement gets fewer constraints from the grid. On frontside PDN you often align macros to the strap pattern and leave channels for straps. With backside power, those front-side constraints relax, though macros still need their own backside connection plan.
• Bump planning changes. Power bumps are on the back; signal I/O may still be on the front or routed through. Packaging and floorplan teams have to agree early.

2. Power grid design and IR/EM#

• Lower resistance from bump to cell is the main win, since the current no longer climbs down the whole front stack.
• The grid is still a design problem. Backside metal pitch, density limits, via/contact rules and pad pitch decide how strong your grid is. Hot spots still exist.
• IR and EM analysis must model both sides. Your extraction and power-integrity tools need the backside stack in the tech file. Ask your vendor whether the backside is modelled with the same accuracy as the front.

3. Placement#

• Utilization can go up. Free front tracks and no front rails/straps blocking pins usually mean less congestion at the same density, which is where reported "compaction" figures come from.
• New legality rules may appear. If nano-TSVs or backside contacts must land at particular positions in the row, the placer has to respect them, just as it respects tap cells today.
• Cell heights may shrink. Removing front rails from the cell is one way processes reduce cell height. That changes pin density and therefore pin access — see our congestion guide.

4. Clock tree synthesis#

• Clocks benefit from free upper front layers. Many teams route clock trunks on thick upper layers; with power gone from those layers there is more room.
• Backside clock routing is a research direction. Several papers study putting clock nets on backside metal too (for example the Georgia Tech work cited below). If your process allows it, CTS has to decide which nets go back and which stay front, and the backside clock competes with the power grid for the same metal.

5. Routing#

• More front tracks for signals.
• Fewer power-strap-induced DRCs and pin-access problems near rails.
• If backside signals are allowed, the router must handle front-to-back connections, which are expensive and limited.

6. Thermal and reliability#

• Thinned silicon and a bonded carrier change the heat path. Heat from the devices now flows through a different stack. Thermal analysis should be part of signoff, not an afterthought.
• Test and debug change too. Intel's newsroom article notes that a two-sided chip needed a rethink of how it is tested; failure analysis that used to look through the back of the die has to adapt.

PDN-first vs PDN-last#

In a conventional flow, the power grid is built first, because the placer and router have to work around it. Park et al. (Georgia Tech, DAC 2025) propose a BS-PDN-last flow for designs that also use backside metal for clocks: reserve regions on the backside with routing blockages, do placement, CTS (including backside clock) and signal routing, and only then convert the reserved regions into the power grid, filling the remaining backside metal (paper). They report it reduces the conflict between IR drop and performance in their experiments.

Whether your production flow can do this depends on your tools and foundry rules, but the idea is useful: once power no longer blocks front-side routing, the order of flow steps is a design choice again.

A worked thought experiment (illustrative)#

Take a block that on a frontside-power node used about 20% of the tracks on two intermediate layers for power straps (an illustrative number; real numbers vary widely). Moving power to the backside gives back those tracks. If routing congestion was the limit on utilization, the block could be placed denser or routed with fewer detours. If timing was the limit, the extra tracks can carry wider or shielded clock and critical nets. If IR drop was the limit, the lower-resistance path from bump to cell reduces the voltage margin you must reserve.

The practical point is to decide which of those three is your bottleneck before you claim a benefit. Don't assume every block gets every gain.

Checklist before starting a backside-power block#

1. What exactly is on the backside: only power, or also clock/signal?
2. What are the backside connection rules (nTSV / contact sites) and how does the placer enforce them?
3. Is the backside stack in your extraction, IR/EM and thermal decks, and is it correlated to silicon data?
4. How does the PDN generator describe backside straps and pads in your P&R tool?
5. How does package and bump planning change?
6. Which test and debug methods change?
7. Have you re-tuned target utilization and congestion settings instead of copying them from the frontside flow?

Mistakes to avoid when moving a flow to backside power#

• Copying frontside utilization targets. A frontside block that closed at a given density was limited by its strap pattern. Re-explore utilization instead of reusing the number.
• Keeping old strap-aware placement settings. Settings that kept cells away from straps or reserved channels for power may now waste area. Review every power-related placement constraint.
• Treating the backside as invisible to timing. If any clock or signal uses backside metal, it has its own RC and coupling, and it shares space with power. It must be extracted and timed like any other layer.
• Leaving thermal to the package team. The thinned, bonded wafer changes how heat leaves the device layer. Bring thermal analysis into block-level signoff.
• Assuming the old ECO tricks still apply. Many late fixes (adding a strap, moving a power via) are now done on a different side with different rules. Find out early what a late PDN ECO looks like.
• Forgetting antenna and reliability checks for the new layers. New metal means new rules; ask whether antenna-style checks apply during backside processing (see our antenna effect guide for the frontside version).

Interview questions and answers#

Q1. What is backside power delivery? Delivering power to the transistors from the back of a thinned wafer through backside metal and nano-scale vias or contacts, instead of down the front-side metal stack.

Q2. Why does it reduce IR drop? The current path from bump to cell is shorter and uses coarse, low-resistance backside metal instead of climbing down many thin front-side layers and vias.

Q3. How does it help routing? Power straps and rails no longer use front-side tracks, so more tracks are available for signals and there are fewer pin-access conflicts near rails.

Q4. Name two companies with announced backside-power processes. Intel (PowerVia, 18A) and TSMC (Super Power Rail, A16).

Q5. What is a buried power rail? A power rail placed below the device level (in the front-end), which can be reached from the back by nTSVs. It is one of the approaches imec has described.

Q6. What new challenges does BSPDN bring to PD? New tech files and PDN commands, placement legality for backside connections, two-sided IR/EM/thermal analysis, changed package and bump planning, and test/debug changes.

Q7. What is a PDN-last flow? A flow that reserves backside regions early and builds the backside power grid after placement, CTS and routing, so power uses the remaining metal.

FAQ#

Does backside power remove the need for IR-drop analysis? No. It reduces resistance, but grids, pads and hot spots still need full IR/EM signoff.

Will standard cells change? They can. Without front rails inside the cell, processes can change cell architecture and height. Get the new library early and check pin access.

Is backside power only for 2nm-class nodes? Today's announcements pair it with gate-all-around nodes (Intel 18A, TSMC A16). See our post on IBM's 2nm chip for background on GAA.

Can I try it with open tools? Some academic flows model backside metal using modified tech files, but public open PDKs with real backside power are rare. Treat any open-source experiment as a model, not a process.

Summary#

• BSPDN moves power to the back of the wafer and leaves the front stack mostly for signals.
• The main PD gains are lower IR drop, freed routing tracks and potentially denser placement; vendor-reported numbers are design-specific.
• Floorplanning, the PDN script, placement legality, CTS options, IR/EM/thermal signoff and packaging all change.
• Because power no longer blocks front routing, flows like PDN-last become possible.

References#

• Intel, "Intel 18A" process page: https://www.intel.com/content/www/us/en/foundry/process/18a.html
• Intel Newsroom, "With PowerVia, Intel Achieves a Chipmaking Breakthrough": https://www.intel.com/content/www/us/en/newsroom/news/powervia-intel-achieves-chipmaking-breakthrough.html
• TSMC, 2024 North America Technology Symposium press release: https://pr.tsmc.com/english/news/3136
• imec, "Backside power delivery": https://www.imec-int.com/en/articles/how-power-chips-backside
• Park et al., "BS-PDN-Last: Towards Optimal Power Delivery Network Design With Multifunctional Backside Metal Layers," DAC 2025: https://gtcad.gatech.edu/www/papers/Park-DAC25.pdf