Level Shifters in VLSI: Multi-Voltage Design, Placement and STA

A level shifter is a cell that passes a signal from one supply voltage to another. Any chip that runs different blocks at different voltages needs them: a CPU cluster on a scalable rail, an always-on controller at a fixed low voltage, I/O and analog interfaces at their own levels. They look simple in a netlist, but they touch power intent, library characterisation, placement, secondary power routing, multi-voltage timing and low-power verification.

This guide covers level shifters from a physical design and sign-off point of view: why they are needed, how the common circuits work, how UPF tells the tools where to put them, how to place and route them, how they are timed across voltage corners, and how to debug the usual problems. All numbers in the worked examples are illustrative, not from any specific library or foundry. Related reading on iVLSI: Power Gating in VLSI, Unified Power Format (UPF), Power in VLSI Physical Design, Timing Library (.lib) and Static Timing Analysis (STA) in VLSI.

Why designs use multiple voltages#

Dynamic power scales with the square of the supply voltage, but logic is slower at a lower voltage. Multi-voltage design uses that trade-off block by block:

• Multi-supply voltage (MSV). Each block gets a fixed voltage that matches its performance need. A high-speed core may run at a higher rail while slow peripherals run lower.
• Dynamic voltage and frequency scaling (DVFS). A block's voltage and clock change at run time with the workload.
• Power gating. A block is switched off completely. If it also runs at a different voltage, its boundary needs both isolation and level shifting. See Power Gating in VLSI.

Every signal that crosses from one voltage domain to another is a candidate for a level shifter. Each domain of a multi-voltage block is usually given its own placement region, often called a voltage area (the exact name depends on the tool).

What goes wrong without a level shifter#

Low to high (L2H)#

Suppose a gate in a 0.6 V domain drives an inverter in a 0.9 V domain. When the driver outputs logic 1, the receiver's input sits at 0.6 V, but its PMOS source is at 0.9 V. The PMOS gate-source voltage is only 0.3 V below its source instead of 0.9 V, so the PMOS is not firmly off.

Worked example A: the half-on PMOS (illustrative)#

Assume VDDL = 0.6 V, VDDH = 0.9 V, and a PMOS threshold magnitude of about 0.3 V.

• Receiver input at logic 1 = 0.6 V. PMOS |Vgs| = 0.9 − 0.6 = 0.3 V, which is at the threshold.
• The PMOS conducts a significant current while the NMOS is fully on. That is a static crowbar current from VDDH to ground for as long as the input stays high.
• The output low level is pulled up by the fighting PMOS, so the noise margin shrinks, and the next stage sees a slow and weak transition.

With a larger gap the receiver may not switch at all. So low-to-high crossings always need a level shifter, even when simulation shows the logic "works" at a typical corner.

High to low (H2L)#

A 0.9 V signal driving a 0.6 V receiver does switch the receiver fully, because the input swing is larger than the receiver needs. Functionally, this often works. Many flows still insert H2L shifters, or at least review these crossings, for several reasons:

• The receiving cell may only be characterised for inputs up to its own supply, so that arc is not properly modelled.
• Input voltage above the receiver supply can stress the gate oxide or forward-bias protection structures, depending on the process and cell design.
• An H2L buffer powered from the receiving rail gives a clean, correctly characterised edge in the receiving domain.

Whether H2L shifting is required is a library and methodology decision. UPF lets you write rules for low-to-high only, high-to-low only, or both, and the low-power checker will flag whichever crossings the rules require.

Level shifter circuits#

The cross-coupled low-to-high shifter#

The classic L2H shifter is a cross-coupled (differential cascode voltage switch style) circuit:

• An input inverter powered by VDDL makes the complement of the input, so the core gets both IN and IN_B at low swing.
• Two NMOS pull-downs are driven by IN and IN_B. Their gates only need the low swing to turn on fully, because NMOS gate-source voltage is referenced to ground.
• Two cross-coupled PMOS loads powered by VDDH latch the full high swing. When one side is pulled down, it turns on the opposite PMOS, which pulls the other side up to VDDH and turns its own PMOS off.
• An output buffer on VDDH drives the load.

The NMOS must be strong enough to overpower the PMOS that is still on at the start of each transition. This contention is the reason L2H shifters are larger and slower than ordinary buffers, and why their delay rises steeply as VDDL falls toward the transistor threshold. The cell therefore has a minimum VDDL (and a maximum VDDH) at which it is guaranteed to work. The library declares that range, and the low-power tools check it.

From a PD point of view the key facts for any L2H topology are the same: the cell needs both supplies, it has a voltage range, and its timing depends on both voltages.

High-to-low shifters#

An H2L shifter is usually a buffer powered by the low rail whose input transistors tolerate the higher input voltage. It needs only one supply, so some libraries let it sit in the receiving domain like an ordinary cell. Many libraries also offer bidirectional or dual-type cells that work as either L2H or H2L across a range, which is useful when DVFS can reverse the relationship between two rails.

Enable level shifters and isolation#

If the source domain can be powered off, the shifter's input floats when that domain is off. A floating input on the cross-coupled core can leave it half-switched and drawing current, and its output is undefined. There are two common fixes:

• Isolate first, then shift. Put an isolation cell, powered by an always-on supply at the source voltage, ahead of the shifter, so the shifter always sees a defined level.
• Use an enable level shifter (ELS). A combined cell that shifts and clamps in one: when its enable is asserted, the output is forced to a known value regardless of the input. It needs both supplies, and the enable comes from the always-on power controller.

Telling the tools: UPF and Liberty#

Power intent in UPF (IEEE 1801) describes the domains, their supplies, and the rules for level shifting. The snippet below is a simplified illustration. Command options differ between UPF versions and tools (for example, later UPF versions moved cell mapping toward a more general interface-cell command), so check your tool documentation before using it.

# Illustrative UPF (simplified) for a low-voltage domain PD_LV create_power_domain PD_TOP create_power_domain PD_LV -elements {u_periph} # Shift every signal entering PD_LV from a higher rail, # and every signal leaving PD_LV to a higher rail set_level_shifter LS_LV_IN -domain PD_LV \ -applies_to inputs -rule high_to_low -location self set_level_shifter LS_LV_OUT -domain PD_LV \ -applies_to outputs -rule low_to_high -location parent

Key options:

• -applies_to selects inputs, outputs or both of the domain.
• -rule selects low_to_high, high_to_low or both.
• -location says which side of the boundary the cell goes: in the domain itself (self), in the domain above it (parent), or at each receiver (fanout).
• -threshold lets you ignore small differences between two supplies, so crossings with a negligible voltage gap are not shifted.

On the library side, Liberty marks shifters with attributes such as is_level_shifter : true and level_shifter_type (low-to-high, high-to-low or both), and declares the valid ranges with input_voltage_range and output_voltage_range. The cell's power pins say which rail powers the input stage and which powers the output, and enable shifters have an enable pin attribute. Tools use these attributes to pick legal cells; if they are missing or wrong, the tool inserts nothing or an illegal cell.

Choosing the location#

Worked example B: one shifter or one per receiver? (illustrative)#

A control signal leaves a 0.6 V domain and fans out to four flops spread across a 0.9 V domain.

• One shifter at the boundary (location parent or self). One cell, one secondary power connection, and the long routing to the four flops is done at full 0.9 V swing with normal buffers. This is usually the best choice.
• One shifter per receiver (location fanout). Four cells, and the long route from the boundary to each shifter is done at the 0.6 V swing on the low-voltage side. That route is slower, more noise- and IR-sensitive, and needs low-rail buffers inside the high-voltage area.

Fanout placement mainly makes sense when branches go to domains at different voltages.

The general rule: keep the low-swing side of the shifter short, place the shifter close to the domain boundary, and do the long distance at the stronger side.

Placement and power routing#

A cell that needs two supplies has to get both of them physically. Libraries solve this in a few ways:

• Single-height cells with a secondary power pin. The cell sits in a normal row of one domain and takes its primary rail from the row. The other supply comes in through a secondary power pin that the router connects to a nearby strap or stripe of the other domain.
• Double-height or special-row cells that carry both rails in the cell structure, placed in a dedicated row or band near the boundary.

Practical points:

• Know which rail is primary. For many L2H cells the output (high) rail is primary and the input (low) rail is secondary, so the cell sits in the high-voltage area and needs a low-rail strap nearby. Other libraries do the reverse. The UPF -location and the cell's primary rail must agree, or the cell ends up in a row with the wrong supply.
• Provide straps for the secondary rail. Without a nearby strap, secondary PG routing makes long thin connections that fail IR/EM or don't route. Plan stripes of the other supply along the boundary band.
• Keep shifters near the boundary with a placement bound or band.
• Watch feedthroughs. A net passing through a domain at a different voltage can pick up buffers from that domain and create unintended crossings. Route it over unbuffered, or buffer it with cells on the correct (often always-on) supply.
• Don't let optimisation break the rules. Sizing, buffering and ECOs must use cells from the correct domain on each side. Re-run the low-power checks after every optimisation step and every ECO; see ECO in VLSI Physical Design.

Timing level shifters across voltage corners#

A level shifter's delay depends on both its input and output voltages, so it must be characterised for every voltage pair the design uses. With DVFS, that set grows quickly: if one domain has three operating points and its neighbour has two, the shifters between them see up to six voltage combinations, each at several process and temperature corners.

Worked example C: a crossing at two DVFS points (illustrative)#

A path launches from a flop in domain A (scalable rail), passes through an L2H shifter, and is captured in domain B at a fixed 0.9 V. Clock period at the capture side is 2.0 ns.

The shifter's delay grew much faster than the logic delay as the input rail dropped (the contention effect), and a path that passes at the nominal point fails at the low DVFS point. Every operating point needs its own timing scenario, with the shifter library for that exact voltage pair.

Other timing points:

• Clock crossings. If a clock passes through a shifter, the shifter's delay varies differently with voltage than the rest of the tree, so inter-domain skew changes between DVFS points. Balance clock paths across domains per scenario, and keep in mind that common-path pessimism removal only helps on the shared part of the tree. See OCV, AOCV and POCV in STA.
• Hold is often worst at the high-voltage points and setup at the low ones, so fixes must hold across scenarios.
• IR drop on either rail moves the shifter's delay. Dynamic IR analysis should include both supplies; see IR Drop Analysis in VLSI.

Sign-off checks for level shifters#

• Missing shifters. Every crossing that the UPF rules require is shifted.
• Redundant or wrong-type shifters. No shifter on a crossing that doesn't need one, and no H2L cell on an L2H crossing (this can happen after DVFS states are added).
• Voltage range. Every shifter's actual input and output voltages, in every power state, fall inside its library range.
• Supply connectivity. Primary and secondary power pins are connected to the correct supply nets, and LVS understands both.
• Isolation and shifting order. Crossings from switchable domains have isolation before the shifter or an enable shifter, and the enable comes from an always-on source.
• Always-on buffering. Shifter enables and other control signals that pass through switchable regions use always-on cells; see the AON Cell basics.
• Timing in every scenario, including the shifter characterisation for each voltage pair.

Debug flowchart: level shifter problems#

1. Start from the low-power static checker. It lists missing, redundant and illegal shifters.
2. Missing shifter? Check that the UPF rule covers the crossing (applies_to, rule, threshold) and that both domains have resolved supply voltages for every power state.
3. Shifter not inserted even though the rule is right? Check the Liberty attributes and voltage ranges. If no cell in the library is legal for that voltage pair, the tool cannot insert one.
4. LVS or secondary-pin errors? Check that a strap of the secondary supply is reachable from the placed shifter, and that the cell's primary rail matches the row it sits in.
5. X propagation or leakage in simulation when a domain is off? Look for a plain shifter fed by a switchable domain without isolation in front of it.
6. Timing fails at one DVFS point only? Confirm that the scenario uses the right shifter library for that voltage pair, then shorten the low-swing side of the path or move logic to the faster side.

Interview Q&As#

Q1. Why is a level shifter needed for a low-to-high crossing? Because a low-swing logic 1 does not turn off the receiver's PMOS fully. The receiver draws static crowbar current, loses noise margin and may not switch correctly at all corners.

Q2. Is a high-to-low shifter always required? Not always. A high-swing input switches a low-voltage receiver, but library characterisation, input voltage tolerance and methodology often require H2L cells or a review of those crossings. The UPF rules decide which crossings get them.

Q3. Explain the cross-coupled L2H level shifter. An input inverter on VDDL creates IN and IN_B. Two NMOS driven by these pull down one side or the other, and two cross-coupled PMOS on VDDH latch the full swing. The NMOS must overpower the PMOS during switching.

Q4. Why is an L2H shifter slow at low input voltage? Its NMOS gate drive is set by VDDL. As VDDL approaches the threshold, the NMOS gets weak while the PMOS it fights is driven by the full VDDH, so the contention lasts longer and delay rises steeply.

Q5. What is an enable level shifter? A combined level shifter and isolation cell. When the enable is active it clamps the output to a defined value, so it can sit on outputs of a domain that may be powered off.

Q6. Why can't a plain shifter be fed directly by a switchable domain? When the source is off, the shifter input floats, which can leave the shifter half-switched and drawing current, with an undefined output.

Q7. How does DVFS affect level shifter timing? Shifter delay depends on both rails, so each operating-point combination needs its own characterised library and timing scenario. A path can pass at one DVFS point and fail at another.

FAQ#

Is a level shifter the same as an isolation cell? No. A level shifter changes the voltage level of a signal between powered domains. An isolation cell clamps the output of a domain that may be off. Enable level shifters combine both functions.

Where can I read more? The IEEE 1801 (UPF) standard defines the power-intent commands, the Liberty reference manual documents the level shifter attributes, and the Low Power Methodology Manual by Keating, Flynn, Aitken, Gibbons and Shi (Springer, 2007) covers multi-voltage design and level shifting.

Summary#

• Level shifters move signals between voltage domains. Low-to-high crossings always need them; high-to-low crossings need them when the library and methodology say so.
• The classic L2H shifter is a cross-coupled circuit that needs both supplies and slows down sharply as the input voltage falls.
• Crossings from switchable domains need isolation ahead of the shifter or an enable level shifter.
• UPF set_level_shifter rules (applies_to, rule, location, threshold) and Liberty attributes together decide what gets inserted and where.
• Place shifters near the boundary, keep the low-swing side short, and plan straps for the secondary supply.
• Time every voltage pair and DVFS point, and re-run low-power static checks after every optimisation and ECO.