Semiconductor and system design services company MosChip Technologies Limited today launched a 28nm multi-protocol long-range (LR) 8G SerDes PHY. MosChip has more than 20 years of track record in designing semiconductor IP, products and SoCs for IoT, networking, industrial and consumer applications.
MosChip is the first fabless semiconductor company in India and has developed many connectivity related products that are manufactured in leading foundries and shipped in millions of units. With the acquisition of Gigacom in 2018, the company has accumulated extensive expertise in analog, mixed-signal design, high-speed serial interfaces, and IP product portfolios (including silicon-proven SerDes, PLLs, and data converters). Multi-channel multi-protocol LR 8G PHY IP is part of MosChips’ high-performance multi-rate transceiver product portfolio to meet the growing demand for small size, low power consumption and low latency edge applications.
“Our LR 8G PHY is implemented as an independent protocol-independent physical media attachment (PMA) IP, with flexible digital I/F on the system side, compatible with most of the PCS standard definitions that exist in the industry today” Chief Architect of MosChip Albert Vareljian said. “The PHY is based on our innovative self-tuning architecture and fully adaptive continuous time equalizer, with automatic gain control analog front end (AFE) combined with adaptive multi-tap decision feedback equalization (DFE) to cover channel changes and PVT range.”
The PHY can be fully configured as programmable channel enable/disable and pre-configured macro selections for 1 to 16 channels, and supports various debugging functions such as serial and parallel loopback. 8G PHY is macro backward compatible and can operate in accordance with PCI Gen1/2 and SATA 1/2 specifications. It includes a PCIe standard multi-channel interface. No external passive components are required, saving system-level area and chip-level pin count.
“This is an important milestone for MosChip, and it highlights our strategic focus on developing a niche SerDes PHY IP that can be customized for customer end applications,” said MosChip MD/CEO Venkata Simhadri. By adding the silicon-proven LR 8G PHY to our product portfolio, we can provide customized/portable PHY IP services and turnkey mixed-signal ASIC solutions.
LR 8G PHY macro deliverables include a complete set of logical views, physical views, documents, Verilog models, UVM-based verification environment, abstract views, free files, netlists, GDSII, and flip chip bump/ball diagram plans.
