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Cadence completes the acquisition of NUMECA

Cadence completes the acquisition of NUMECA. Cadence Design System Co., Ltd. (NASDAQ: CDNS) today announced that it has completed the acquisition of NUMECA International. The addition of NUMECA's technology and talents has provided support for the Cadence® Intelligent System Design™ strategy and expanded its system analysis product portfolio with computational fluid dynamics (CFD) solutions.

  • VLSI NEWS
Cadence completes the acquisition of NUMECA

Cadence Design System Co., Ltd. announced that it has completed the acquisition of NUMECA International. The addition of NUMECA's technology and talents has provided support for the Cadence® Intelligent System Design™ strategy and expanded its system analysis product portfolio with computational fluid dynamics (CFD) solutions.

These products will provide first-class Cadence system analysis solutions for integrated circuits (IC), electronic subsystems and complete system designs. NUMECA's proven technology provides services for multiple industries such as aerospace, automotive, industry, and navigation, and has been adopted by industry leaders such as NASA, ArianeGroup, Honda, and Ford.

About Cadence

With more than 30 years of computing software expertise, Cadence is a key leader in the field of electronic design. The company uses its basic intelligent system design strategy to deliver software, hardware and IP, thereby turning design concepts into reality. Cadence’s customers are the most innovative companies in the world. They provide extraordinary electronic products, from chips to circuit boards to systems suitable for the most dynamic market applications, including consumer, hyper-scale computing, 5G communications, automotive, mobile, Aerospace, industry and healthcare. For six consecutive years, "Fortune" magazine selected Cadence as one of the 100 best companies to work for.

Written by

Swasti Pujari

Associate Director, Backend Engineering at CoreIC Technologies, with 15+ years in VLSI Physical Design and backend engineering. Previously Practice Head at UST Global, leading Physical Design, STA, EMIR, DFT, and Physical Verification. Delivered 3nm, 6nm and 7nm projects for AMD, Intel, and Microchip, and published IEEE research on hybrid AI-EDA floorplanning.