Cadence expands cooperation with TSMC and Microsoft to accelerate the timing approval of Giga-level designs in the cloud

Cadence Design Systems, Inc. announced the results of a tripartite collaboration with TSMC and Microsoft in 2021. The focus of the collaboration is to use cloud infrastructure to accelerate the digital timing approval of 1+ billion transistor designs. These large designs are at the core of advanced applications such as hyperscale computing, graphics, and machine learning (ML) applications. Given the huge scale of these designs, engineering teams continue to face the challenge of meeting schedules and calculating budgets. Through this cooperation, ordinary customers can use the ready-to-use Cadence CloudBurst™ platform and Microsoft Azure Cloud to use the Cadence® Tempus™ timing sign-off solution and TSMC technology to speed up sign-off progress and reduce computing costs.

Suk Lee, vice president of TSMC’s Design Infrastructure Management Department, said: “Semiconductor designers have been pushing boundaries to create larger and larger designs. It is important for design teams to meet their tight product schedules.” Over the past year, we have worked closely with Cadence and Microsoft through the TSMC OIP Cloud Alliance, giving our mutual customers access to our advanced technology, Cadence sign-off solutions and cloud product portfolio, as well as Microsoft’s Azure platform to seamlessly handle gigabit Class design and quickly bring differentiated products to the market. ”

Mujtaba Hamid, general manager of Microsoft Azure Silicon, Modeling and Simulation, added: “Microsoft’s Azure cloud platform enables HPC customers to break through the possibilities of silicon design sign-off and other demanding scenarios. Our collaboration with Cadence and TSMC continues to pave the way for accelerating silicon design through the cloud, enabling the industry to provide the highest quality products and achieve time-to-market goals. ”

Timing sign-off in the gigabit design cloud

In order to solve the sign-off problem of gigabit designs, the Cadence Tempus timing sign-off solution uses a massively parallel architecture called Distributed Static Timing Analysis (DSTA). DSTA is production-proven in the cloud of large-scale TSMC advanced node tapeouts and provides the scalability required to sign the world’s largest design. Using DSTA, Cadence demonstrated a method that, compared with the traditional non-distributed STA method, can minimize the computational cost and complete the timing of 10+ billion transistor designs in hours instead of days. Sign off. For customers who want to focus on excellent design and PPA benefits instead of spending energy on IT setting and protecting the cloud environment, the Cadence CloudBurst platform provides a complete design process or peak demand requirements for specific functions, such as timed sign-offs.

“Through continuous cooperation with TSMC and Microsoft, we have set a new industry benchmark and improved our customers’ ability to meet their schedules by adopting the Tempus Timing Signoff solution in the cloud,” said Senior Vice President Dr. Chin-Chi Teng. General Manager of Cadence Digital and Signing Group. “The scalability of our software on the cloud and our readily available Cadence CloudBurst environment enable our customers to effectively manage the most time-sensitive and demanding semiconductor design projects.”

The Cadence Tempus timing sign-off solution is part of a broader full-process digital suite that provides customers with a predictable and accelerated path to design closure. The CloudBurst platform provides fast and easy access to Cadence tools and is part of the broader Cadence cloud product portfolio. The digital and cloud product portfolio supports the Cadence Intelligent System Design™ strategy, enabling customers to achieve superior system-on-chip (SoC) design.


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