Swasti Pujari
Practice Head & VLSI Expert
Practice Head at UST Global with 14+ years of VLSI experience, leading backend domains including Physical Design, STA, EMIR, DFT, and Physical Verification. Successfully delivered complex projects for global clients including AMD, Intel, and Microchip, while pioneering AI-EDA research and innovation.
About Me
Professional Journey
With 14+ years of comprehensive VLSI experience, I currently serve as Practice Head at UST Global, leading backend domains including Physical Design, STA, EMIR, DFT, and Physical Verification. My career has been marked by successful delivery of highly complex projects for global clients including AMD, Intel, and Microchip.
As a strong people manager, I focus on mentoring associates, building high-performing teams, and representing UST in client meetings. I'm actively contributing to the future of semiconductor design through AI-EDA research, including a published IEEE paper on hybrid AI-EDA approaches.
Location
Bengaluru, India
Current Role
Practice Head at UST Global
Quick Facts
Experience
14+ Years VLSI
Research
IEEE Published
Expertise
VLSI Backend Domains
Innovation
AI-EDA Research
Technical Expertise
Backend Domains Leadership
Leading Physical Design, STA, EMIR, DFT, and Physical Verification
AI-EDA Research
Published IEEE paper on hybrid AI-EDA approaches for VLSI floor planning
Global Client Management
Successfully delivered complex projects for AMD, Intel, Cisco, IBM and Microchip
People Management
Mentoring associates, building high-performing teams, and client representation
Business Alignment
Working with Sales, TA, and Operations for revenue growth and expansion
Technical Writing
Regular contributor of semiconductor blogs on UST portal and published IEEE research papers
Technical Skills & Tools
EDA Tools
Technologies
Programming
AI/ML Tools
Professional Experience
Practice Head
UST Global, Bengaluru
Aug 2024 - Present
Leading backend domains including Physical Design, STA, EMIR, DFT, and Physical Verification. Representing UST in client meetings, working with Sales/TA/Operations for business expansion, and supporting US team hiring.
Technical Lead
UST Global, Bengaluru
February 2023 - Aug 2024
Promoted to Technical Lead in recognition of leadership and consistent impact. Led complex semiconductor projects and mentored associates while building strong client relationships.
Senior Engineer
SeviTech Systems Pvt. Ltd. (UST Global), Bengaluru
April 2021 - February 2023
Delivered multiple projects on 3nm, 6nm, and 7nm technologies for AMD, Intel and Microchip clients. Managed team of 9 members on Intel 7nm project.
Senior Physical Design Engineer
Synapse Design Automation, Penang, Malaysia
Jan 2020 - Aug 2020
8 months of international experience in Physical Design, working on advanced semiconductor projects in Malaysia.
Physical Design Engineer
eInfochips Ltd., Bengaluru
Nov 2018 - Nov 2019
Worked on 28nm technology projects, responsible for complete Physical Design flow from Floor planning to Signoff.
Physical Design Engineer
Cyient (Infotech Enterprises) Limited, Hyderabad
July 2011 - Aug 2014
Built foundational expertise in Physical Design, working on 45nm TSMC technology projects and learning complete design flow.
Achievements & Research
Rapid Career Growth
Promoted twice in 18 months: Senior Engineer → Technical Lead → Practice Head
Technology Leadership
Leading backend domains across 3nm-45nm technologies for Fortune 500 clients
Research Excellence
IEEE published research on AI-EDA approaches with ongoing innovation projects
Leadership & Recognition
Career Progression Excellence
Rapid promotion track demonstrating exceptional performance and leadership capabilities
Client Success & Delivery
Consistent delivery excellence for global semiconductor leaders
Team Leadership Excellence
Building and leading high-performing engineering teams
Thought Leadership
Industry recognition through technical content and knowledge sharing
Research & Innovation
IEEE Publication
Research paper on hybrid AI-EDA approaches for VLSI planning
Ongoing Research
Multiple research papers on AI and Semiconductor technologies
AI-EDA Innovation
Proof-of-concept AI-based Physical Design Resources Agent
Future-Ready Expertise
Pioneering next-generation semiconductor design methodologies
Impact Metrics
Key Projects
3nm SOC Design
May 2023 – November 2023
Block Level Ownership for SOC design implementation with 3nm TSMC foundry. Responsible for Floor planning, place & route, and timing closure of rectangular block design.
Business Impact:
- • Achieved 15% power reduction through innovative floor planning
- • Enabled client's next-generation product launch timeline
Tools: Innovus, Tempus | Team Size: 5 engineers
6nm High-Frequency Block Design
October 2022 – April 2023
Block Level Ownership with 6nm TSMC foundry. Complete responsibility from Floor planning to signoff including DRC/LVS closure, antenna checks, and timing ECO implementation.
Business Impact:
- • Achieved 1.5GHz frequency target with 20% area optimization
- • Zero post-silicon issues, leading to client contract renewal
Tools: Innovus, Tempus | Team Size: 3 engineers
7nm Intel Team Management
January 2022 – July 2022
Managed team of 9 members on multiple FUBs. Responsible for Placement and Routing, ECOs, Quality checks, Signal Integrity fixes, and milestone closure. Coordinated between client and company for effective project implementation.
Business Impact:
- • Led a complex project with 9-member team across 5 FUBs
- • Achieved 95% team retention and 100% milestone delivery
- • Strengthened Intel partnership, leading to 2 additional projects
Tools: PARADE | Team Size: 9 engineers
6nm Multi-Voltage SOC Design
July 2021 – October 2021
Block Level Ownership from Netlist to GDSII for 2 blocks with multi-voltage designs. Created scope and non-scope power domains with LS regions. Responsible for complete floor planning, place & route, and timing closure.
Key Achievements:
- • Successfully closed tile with all signoff checks
- • Performed CalibreDRC, Interface Antenna, and CalibreERC analysis
- • Executed timing ECOs for setup/hold/cap/trans optimization
Tools: ICC2 | Blocks: 2 blocks
28nm High-Density Block Design
September 2019 – November 2019
Block level Floor Planning to Placement for high-density design with 104 macros and 1 million instances. Initial utilization of 72.6% with 1 GHz frequency target.
Design Complexity:
- • 104 macros with 1 million instances
- • High initial utilization of 72.6%
- • 1 GHz frequency requirement
Tools: Innovus | Macros: 104
16nm Large-Scale SOC Design
December 2018 – May 2019
Block level Floor Planning to Signoff for large-scale design with 2.3 million instances. Initial utilization of 66.8% with 1 GHz frequency target.
Scale & Performance:
- • 2.3 million instances design
- • 66.8% initial utilization
- • Complete floor planning to signoff responsibility
Tools: ICC2 | Instances: 2.3M
45nm Advanced Physical Design
July 2013 – February 2014
Block level Floor Planning to Routing for 45nm design with 90 macros and 0.9 million instances. Complete physical design flow implementation.
Technical Scope:
- • 90 macros with 0.9 million instances
- • Complete floor planning to routing flow
- • Advanced 45nm technology node
Tools: IBM Cu-45nm | Macros: 90
45nm Complete Design Flow
August 2012 – April 2013
Complete Physical Design flow from Floor planning to Signoff. Responsible for DeCaps placement, Clock Tree Synthesis, timing closure, and DRC/LVS fixes.
Complete Flow:
- • Floor planning, DeCaps placement, CTS
- • Setup/hold timing closure and optimization
- • Timing and SI driven routing with DRC/LVS fixes
Tools: IBM Chipbench, Chipedit, Einstimer | Macros: 45
45nm Foundation Project
November 2011 – May 2012
Test project to understand Physical Design fundamentals. Complete Physical Design flow implementation with square-shaped block design.
Learning Foundation:
- • Complete Physical Design flow understanding
- • 20 macros with 70K instances
- • Square-shaped block design
Tools: IBM ChipBench, Chipedit, Einstimer | Shape: Square
Education & Academic Foundation
Strong academic background in engineering and business administration
Master of Business Administration (MBA)
2014Business Administration
Sikkim Manipal University
Key Focus Areas:
- • Strategic Management & Leadership
- • Business Operations & Analytics
- • Project Management & Team Building
Bachelor of Technology (B.Tech)
2011Instrumentation and Control
Biju Patnaik University
Core Subjects:
- • Control Systems & Automation
- • Instrumentation & Measurement
- • Electronics & Signal Processing
Continuous Learning & Professional Development
Ongoing commitment to staying current with industry trends and technologies
IEEE Publication
Research Paper
Technical Blogging
100+ Published Articles
AI-EDA Research
Innovation Focus
Mentoring
Team Development
What Colleagues Say
Sudhir Bakshi
Account Manager & Client Partner at UST
"I've had the pleasure of working with Swasti Pujari, who leads our Physical Design practice with exceptional expertise and vision. Her strong command over STA, DFT, PD, and hands-on experience with industry tools like ICC2, Innovus, and PrimeTime make her a standout leader. Highly recommended!"
Mamatha Vedamuri
Assistant Manager-TA, UST
"I've had the privilege of working with Swasti at UST and I can confidently say that she is one of the most knowledgeable and strategic leaders in the field of Physical Design. As the Practice Head for Physical Design, she combines technical brilliance with a genuine passion for mentoring and building high-performing teams. She consistently demonstrates outstanding leadership, clear communication, and a strong commitment to company's success."
Srinivas Peyyala
Associate Director, TA
"I had the pleasure of working with Swasti at eInfochips, where she was part of the Physical Design Team. She is technically strong, goal-oriented, and always brings a calm and composed approach to her work. Swasti is a friendly person who effortlessly mingles with everyone, creating a positive and collaborative atmosphere. I enjoyed working with her, as her dedication and positive vibes make her a valuable asset to any team."
Technical Blog Contributions
Sharing knowledge and expertise in semiconductor and physical design domains
Featured Articles for UST Global
Latest insights on VLSI design, AI-EDA, and semiconductor innovation
Revolutionary power optimization techniques transforming VLSI Design in 2025
Exploring cutting-edge techniques for power reduction in modern VLSI design workflows
Timing closure at 3nm and beyond: Techniques, ECO tricks & MCMM secrets
Advanced strategies for achieving timing closure in cutting-edge 3nm technology nodes
AI chips driving the next semiconductor supercycle: Strategic analysis and industry outlook
Strategic insights into the AI-driven semiconductor boom and future market trends
AI in cadence innovus workflows: 10x faster physical design in 2025
How AI integration is revolutionizing physical design workflows and accelerating time-to-market
IVLSI Blog
All technical posts are authored by Swasti Pujari, offering comprehensive insights into semiconductor design, physical design methodologies, and industry best practices. With over 100 published articles, the content is freely accessible to support the global learning community.
Read Blog PostsSemiconductor Design • Physical Design • VLSI • EDA Tools
Educational Content
Comprehensive guides and tutorials for semiconductor professionals
Global Reach
Readers from around the world benefit from the content
Industry Insights
Latest trends and best practices in VLSI and physical design
Let's Connect
Interested in collaborating or learning more about my work? I'd love to hear from you!