Physical Synthesis

What is Physical Synthesis?

To start physical synthesis, we need to have all the inputs like RTL, SDC, timing lib, physical lib, UPF, DEF and other tech files. At this stage, we go for initial placement and trial route after converging the logic level design into circuit level.

Physical synthesis perform the coarse placement with congestion aware and timing aware optimizations. Along with placement, it does trail route which results into better RC correlation with physical design tools. This helps in achieving better congestion, timing and power at later stages of physical design. Performing physical synthesis helps to avoid the additional iterations in the physical design convergence.

Steps in Synthesis

There are basically three steps that happens during the synthesis:

1. Architecture level or High level Synthesis
2. Logic level GTECH optimization
3. Gate Level or Mapping Optimization

Let’s understand more into the steps of the flow.

1. Read Inputs
2. Elaborate
3. Compile
4. Optimization
5. Design for Test (DFT)
6. Quality checks
7. Outputs

1. Read Inputs

At this stage of design all the inputs mentioned above is being read.

2. Elaborate

As we read the RTL and we have only logical information in Boolean expressions, the very first thing tool does is make the building blocks as per the logic present in the RTL. Logically, now tool understands the logic hierarchy and input output of the different hierarchy levels inside the design. The second step tool does is map these building blocks with the inbuilt tool library. These cells are known as GTECH cells. The GTECH cells are technology independent as these are tool inbuilt. RTL codes are mostly written in Boolean expressions. At this stage, these Boolean expressions are converted into cell level using the inbuilt cells.

During elaboration, tool looks if the design and the hierarchy inside the design are unique or not> If unique, then only tool will proceed for further run. Once the run proceeds further, tool looks whether there are any unresolved reference in the design. If no unresolved reference, then tool proceeds further otherwise run stops. In this case, we need to debug the unresolved reference and get the RTL corrected.

Generally, below are the steps tool does to complete the elaborations steps:

1. Configure Timing and Physical Libraries.
2. Set scenario for Timing and Leakage
3. Read RTL
4. Link all the logic groups with the internal tool build libraries. Once linking is done, it will rename the same cells to avoid conflict in the design.
5. Now it instantiates the design and then goes for uniquifying the design.

Elaboration is done.

Once the design is fully loaded and done with elaboration, it looks for timing loops in the design. If any timing loops has been detected, then we need a fix for this or tools sometimes disable the timing loop by disabling the timing arc between input and output pins of a cell (Mostly Buffer {A(input)-Z (Output)}). Let’s understand about timing loops in details and see how to fix it.

There are few cases where we might have the timing path where start point and end point are same, which means it’s a loop. We started from one point and came back to the same point. During the analysis, timing tool generally does not verify this. Timing tool will disable a single timing arc to break this loop.

Once the elaboration run has been completed then we can investigate the log file now. Look for Errors and Warnings present in the log file and clean it. At this stage, mostly the errors and warning will be like missing files, linking issues, timing loops etc. If you are looking for more information on debugging log files, then let me know in the comments section below.

In the beginning we have seen that there are three steps of synthesis, at the elaboration stage architectural level or high level synthesis and GTECH cell optimization happens.

3. Compile

Once we are done with Elaboration and understand the design with the help of GTECH cells, now it’s time to map these cells with the actual cells by the help of library. The choice of cells during the mapping totally depends upon the SDC constraints, user settings (Don’t use cell list) etc. Along with this, tool removes the registers which has constant propagation. Here we need to look at the fact that, whatever registers are getting removed are not actually required. If we need these registers in the design, then we need to do an initial level debug on why constant propagation is happening and we need to send the feedback to the RTL team in order to get the correct RTL.

During compile, the integrated clock gating cells are added in the design. The information regarding clock gating cells are already present in the RTL. We do change it according to proper choice of cells. If you want to understand Integrated Clock Gating in details, you can refer to the below link.

Integrated Clock Gating (ICG) Cell & Related Concepts

Once the mapping is done, now it’s time to go for optimization. Let’s understand the optimization process and the types of optimization that happens during synthesis.