Difference Between Latch and Flip-Flop: Structure, Timing Checks and STA

Every sequential element in a digital design stores one bit, but not every storage element decides when to store it in the same way. A latch is level-sensitive: while its enable (usually the clock) is active, its output follows its input. A flip-flop is edge-triggered: it samples its input only at a clock edge and holds the value until the next one. That single difference changes how the element is built, how static timing analysis (STA) checks it, how much time a path can use, how hold is fixed, and where each one belongs on a chip.

This guide explains the difference between a latch and a flip-flop from a physical design and timing point of view: structure, timing parameters, how STA treats each, where latches still appear, how unintended latches get into a netlist, and how to debug latch timing. It includes illustrative worked examples, a debugging flowchart, interview questions and an FAQ.

Related reading: Static Timing Analysis (STA) in VLSI, Setup and Hold Violations, Time Borrowing (Cycle Stealing) in VLSI and Clock Gating and ICG.

Latch vs flip-flop in one sentence#

A latch is transparent for a whole phase of its enable and opaque for the other phase; a flip-flop is never transparent from input to output, because it captures data at one edge and launches it at that same edge.

• A positive-level latch (also called a high-transparent latch) passes D to Q while the clock is high and holds its value while the clock is low. It closes on the falling edge.
• A negative-level latch (low-transparent) passes D to Q while the clock is low and closes on the rising edge.
• A positive-edge flip-flop samples D at the rising edge only. A negative-edge flip-flop samples at the falling edge.

How a flip-flop is built from two latches#

Most standard-cell flip-flops are master-slave designs: two latches of opposite polarity in series. For a positive-edge flip-flop, the master is a negative-level latch and the slave is a positive-level latch.

• While the clock is low, the master is transparent and follows D. The slave is closed and holds the previous output.
• At the rising edge, the master closes and keeps the value D had just before the edge. The slave opens and passes that value to Q.
• While the clock is high, the master is closed, so changes on D cannot reach Q.

Because the two latches are never open at the same time, there is no transparent path from D to Q. The flip-flop's behaviour collapses onto one instant, the rising edge. That is what makes edge-triggered design easy to reason about and easy to time.

This also explains a practical fact: a flip-flop contains roughly two latches' worth of storage plus the clock inverters that drive them, so a single latch is smaller and presents less clock load than a flip-flop of similar drive. Exact area and power depend on the library, so compare the cells in your own .lib and LEF rather than relying on a rule of thumb.

Waveforms: the same input, two different outputs#

The clearest way to see the difference is to apply the same D waveform to both elements.

In the illustration (ideal, zero-delay waveforms):

• When D rises during a high phase, the latch output rises immediately, while the flip-flop waits for the next rising edge.
• A short glitch on D during a high phase passes straight through the latch. The flip-flop ignores it because it was not sampling at that moment.
• When D changes during a low phase, the latch holds its old value and only follows D when the clock goes high again.

The glitch case matters in practice: a latch is only as clean as the logic feeding it during its transparent phase.

Timing parameters of each element#

Both elements are characterized in the timing library (see Timing Library (.lib)), but the set of arcs differs.

The key point for STA is the D-to-Q arc. A latch is a sequential element when it is closed and something close to a buffer when it is open. Timing tools have to handle both views.

How STA treats flip-flops and latches#

Flip-flops#

For a flip-flop-to-flip-flop path, STA checks setup at the next capture edge and hold at the launching edge, after skew. Nothing crosses the flop. This is the model described in Setup and Hold Violations.

Latches#

For a path that ends at a latch, STA checks setup relative to the closing edge, but it treats the time between the opening and closing edges as usable:

• If data arrives before the opening edge, the latch behaves like a flip-flop. The next path starts at the opening edge (clock-to-Q).
• If data arrives after the opening edge but before closing edge minus setup, the data passes through. The tool reports time borrowing: the amount by which arrival is later than the opening edge. The next path, from the latch output, starts at the actual arrival time plus D-to-Q delay, so it inherits less time.
• If data arrives later than closing edge minus setup, it is a setup violation.

The detailed borrowing arithmetic, including the maximum allowed borrow and how tools report it, is covered in Time Borrowing (Cycle Stealing) in VLSI. The important difference from flip-flops is that a latch makes two consecutive paths share one budget. Slack on one side can absorb a shortfall on the other.

Hold for a latch is checked at the closing edge. The new data must not arrive before the latch has closed on the data it was meant to hold, plus the hold time. This makes hold behaviour depend strongly on the phase relationship between the launching element and the latch, as the next example shows.

Worked example 1: hold depends on phase (illustrative)#

Assume a 2.0 ns clock with a 50% duty cycle, ideal clocks (no skew), clock-to-Q of 0.10 ns and a hold time of 0.03 ns at every capturing element. All numbers are illustrative, not from a real library. A rising-edge flip-flop launches data at time 0, and the path between launch and capture has combinational delay d.

Case A: flip-flop to rising-edge flip-flop. Hold is checked at the same rising edge, t = 0. Arrival is 0.10 + d, and it must be at least 0.03. Any d ≥ 0 passes.

Case B: flip-flop to negative-level latch. A negative latch closes at the rising edge, so its hold check is also at t = 0, the same as case A. This keeps the alternating-phase pattern of master-slave design.

Case C: flip-flop to positive-level latch (same phase). Suppose the design intends the latch to capture this data in the next high phase. The latch is transparent from 0 to 1.0 ns in the current cycle and closes at 1.0 ns on the value it must hold. New data must not reach it before 1.0 + 0.03 = 1.03 ns. With arrival 0.10 + d, the path needs d ≥ 0.93 ns of minimum delay, almost half the cycle.

This is why designers alternate latch phases. Hold buffers can fix case C, but changing the latch polarity or using a flip-flop is usually the real fix.

Worked example 2: borrowing through a latch (illustrative)#

Same 2.0 ns clock and 50% duty cycle. A rising-edge flip-flop launches at t = 0 into logic that ends at a negative-level latch (open from 1.0 to 2.0 ns). The latch drives more logic into a rising-edge flip-flop that captures at t = 2.0 ns. The one-cycle budget is split into two half-cycle stages, but the logic is not balanced. Assume setup of 0.05 ns at the latch and at the capturing flop, and a latch D-to-Q delay of 0.08 ns. All values are illustrative.

• Stage 1 (flop to latch): clock-to-Q 0.10 ns plus logic 1.25 ns, so data reaches the latch at 1.35 ns. The latch opened at 1.0 ns, so the path borrows 0.35 ns. The setup check at the closing edge (2.0 − 0.05 = 1.95 ns) passes with 0.60 ns of slack.
• Stage 2 (latch to flop): the path starts when data leaves the latch, at 1.35 + 0.08 = 1.43 ns. With 0.40 ns of logic it arrives at 1.83 ns. Required time at the capturing flop is 2.0 − 0.05 = 1.95 ns, so slack is 0.12 ns.

Now replace the latch with a falling-edge flip-flop at the same point. Stage 1 must finish by 1.0 − 0.05 = 0.95 ns, but it needs 1.35 ns, so it fails by 0.40 ns even though stage 2 has plenty of spare time. The latch turned a failure into a pass by letting the long stage use time the short stage did not need.

When reading a report, always check the borrow value and the path that starts at the latch: a clean path into a latch can hide a now-critical downstream path.

Where latches appear in real designs#

Most logic uses flip-flops because edge-triggered timing is simpler to constrain, test and close. Latches remain common in specific roles.

Integrated clock gating cells#

A standard integrated clock gating (ICG) cell for rising-edge logic contains a negative-level latch on the enable, followed by an AND gate with the clock. The latch is transparent while the clock is low, so the enable can settle during the low phase. When the clock rises, the latch closes, and the enable cannot change while the clock is high. That prevents a glitch on the gated clock. The tool performs a clock gating setup and hold check on the enable at the ICG. See Clock Gating and ICG and Integrated Clock Gating (ICG) Cell and Related Concepts.

Lockup latches in scan chains#

When a scan chain crosses from flops on one clock to flops on another clock, or between two parts of a clock tree with very different latency, the shift path can fail hold because the receiving flop's clock arrives much later than the launching flop's clock. A lockup latch fixes this. It is a level-sensitive latch clocked by the launching side's clock, transparent in the opposite phase (a negative-level latch for rising-edge flops). It holds the launched value for half a cycle, so the receiving flop can tolerate a late clock without a hold failure. Lockup latches are usually inserted by the DFT tool and must be preserved through placement and scan chain reordering.

Latch-based and high-performance datapaths#

Some high-frequency designs use two-phase latch pipelines. Borrowing absorbs stage imbalance and some clock skew, at the cost of more complex timing, constraints and hold checks. A related technique is the pulsed latch: a latch opened for a short pulse after each edge, which behaves much like a flip-flop with a smaller sequencing overhead but a larger hold requirement because the window is open for the pulse width.

Unintended latches from RTL#

A large share of latch problems in practice are latches nobody wanted. In Verilog, a combinational always block that does not assign a variable on every branch implies memory, so synthesis infers a latch:

// infers a latch on y: no assignment when sel == 0 always @(*) begin if (sel) y = a; end

The fixes are standard:

• Assign a default value at the top of the block, or cover every branch (else, default in case).
• In SystemVerilog, use always_comb for logic intended to be combinational and always_latch only for intended latches. The language standard (IEEE 1800) expects tools to flag a latch inferred inside always_comb.
• Review the synthesis log: tools report inferred latches. Treat every unexpected one as a bug until proven otherwise.

An unintended latch is risky for timing (its paths may not be constrained as intended) and for test (plain latches are not part of mux-scan chains and can reduce coverage unless made transparent in test mode).

Physical design and CTS considerations#

• Clock duty cycle matters for latches. A flip-flop mostly cares about the active edge. A latch's transparent window is the clock's pulse width, so duty-cycle distortion through the clock tree directly shrinks or grows the window available for borrowing. Check Duty Cycle and Minimum Pulse Width and minimum pulse width checks on latch clock pins.
• CTS treats latch clock pins as sinks. Balance them with the flops they talk to, and remember that skew changes both the opening and closing edges.
• Useful skew behaves differently. With latches, borrowing already moves slack between stages automatically. See Useful Skew.

Debugging latch-related timing problems#

1. Inferred by accident? Fix the RTL and re-synthesize. Do not try to time an accidental latch into closure.
2. Intentional? Confirm the cell type and polarity match the clock it sits on.
3. Borrowing leaves the next stage short? Read the borrow value and the path starting at the latch output, and speed up the path into the latch.
4. Hold fails at the closing edge? Check the phase relationship. Alternating phases usually beats inserting many hold buffers.
5. Transparent window wrong? Check duty cycle and minimum pulse width at the latch clock pin after CTS.
6. Latch loop or unexpected arc? Check constraints and the tool's latch analysis settings against the design intent.
7. Re-run STA and review the borrowing report again.

Interview questions and answers#

Q1. What is the main difference between a latch and a flip-flop? A latch is level-sensitive and is transparent while its enable is active. A flip-flop is edge-triggered and samples its input only at a clock edge.

Q2. How is a positive-edge flip-flop built from latches? A negative-level master latch followed by a positive-level slave latch on the same clock. The master captures while the clock is low; at the rising edge it closes and the slave opens.

Q3. Where are setup and hold checked for a latch? At the closing edge. Data arriving between opening and closing edge (minus setup) still passes and is reported as time borrowing.

Q4. Why can a latch borrow time but a flip-flop cannot? A latch has a transparent window, so late data can pass through and the next stage starts later. A flip-flop samples at one instant, so late data simply misses the edge.

Q5. Why does an ICG cell use a latch? The negative latch holds the enable stable while the clock is high, so the AND gate cannot produce a glitch or a truncated pulse on the gated clock.

Q6. What is a lockup latch? A latch inserted in a scan chain between flops on different clocks or very different clock latencies. It holds the shifted value for half a cycle so the receiving flop does not see a hold violation.

Q7. How does an unintended latch get into a design? Usually from incomplete assignment in combinational RTL, such as an if without else or a case without default. Synthesis infers a latch to remember the old value.

FAQ#

Is a latch faster than a flip-flop? A latch can pass data without waiting for an edge, but whether a latch-based design is faster depends on the whole clocking scheme, duty cycle and hold margins.

Do modern ASICs still use latches? Yes, mainly inside ICG cells, as lockup latches in scan chains, in memories and register files, and in some high-performance or low-power datapaths. General logic is still overwhelmingly flip-flop based.

Does STA handle latches automatically? Modern STA tools analyze latch borrowing by default, but check the tool's settings for maximum borrow and the reports for unexpected latches.

Summary#

• A latch is level-sensitive and transparent for one clock phase; a flip-flop is edge-triggered and never transparent from D to Q.
• A positive-edge flip-flop is a negative master latch followed by a positive slave latch.
• Flip-flops are checked at one edge. Latches are checked at the closing edge, and data in the transparent window passes through as time borrowing, which shifts time to the next stage.
• Latch hold depends on phase: a same-phase flop-to-latch path needs about half a cycle of minimum delay, so alternate phases.
• Latches appear intentionally in ICGs, lockup latches, memories and latch-based datapaths. Unintended latches come from incomplete RTL and should be fixed at the source.
• After CTS, check duty cycle and minimum pulse width on latch clock pins, and always read the borrowing report.

References#

• N. Weste and D. Harris, CMOS VLSI Design: A Circuits and Systems Perspective, 4th ed., Addison-Wesley, 2010 (chapter on sequential circuit design).
• J. M. Rabaey, A. Chandrakasan and B. Nikolić, Digital Integrated Circuits: A Design Perspective, 2nd ed., Prentice Hall, 2003 (chapter on sequential logic circuits).
• IEEE Std 1800, SystemVerilog: Unified Hardware Design, Specification, and Verification Language (always_comb and always_latch).
• Flip-flop (electronics), overview: https://en.wikipedia.org/wiki/Flip-flop_(electronics)