Placement

What is Placement?

Once we are done with the floorplan after placing all the physical cells inside the core boundary, we are left with standard cells which are still sitting out of the core design area. Now we need to place all the standard cell sitting outside this core boundary. Placing of these standard cells is called placement stage. Let’s dig into details.

Standard Cell

• A group of transistors and their interconnect structure which provides all the Boolean logic and Storage functions. A very interesting thing about the standard cell is that all the standard cells have same height but their width can be different. So placement locations are pre-specified on the chip area.
• Standard cells are used to design a huge digital circuit for some particular operations with digital logic features.
• These cells will be used by the designer at Synthesis and Physical design stages. Depending upon the different trade-off requirements, these cells will be used by the designers.

Placement

• Placement is the process of determining the locations of standard cells present in the Netlist by placing these cells inside the core area.
• The cells are logically present in the Netlist. Looking at the physical presence of cells in LEF, tool places at the desired location.
• Placement of cells are most challenging and important phase in PnR. Good placement leads to good routing.
• As we know there are a number of same kind of cells present in the .lib, the tool looks at the logic present in the netlist and pick the cell by taking care of input constraints to meet the trade-off of the design.

Placement Stages

During placement, following three stages happens:

• • Global Placement
  • Refine Placement (Legalization)
  • Detailed Placement

Placement Objectives/Quality Checks

The below placement quality checks need to be done to have a place exit and get a qualitative database of placement.

• Congestion
• Performance (Timing)
• Power
• Routability
• Placement Runtime

1. Congestion

https://ivlsi.com/congestion-vlsi-physical-design/

2. Performance (Timing)

https://ivlsi.com/timing-vlsi-physical-design/

3. Power

https://ivlsi.com/power-in-vlsi-physical-design/

4. Routability

We have placed all the physical and standard cells till now. With the help of trial route (Global Route) we get estimation about the route length and route types of the design. During optimization, we see that tool works on minimizing the route length and optimize the route to the best possible way. Rerouting of the detoured nets which can be optimized are already done and from here we can look for best possible result of actual routing. We have already seen how tool has optimized and done scan reordering. Similarly, for signal/clock route tool tries to optimize to come back with good result.

5. Runtime

•  The partition takes more time to complete the placement of the design if it is big. Big partition means a greater number of standard cells, so to place those cells and optimize to achieve the target, it might take long runtime as compared to small partition.
• Placement runtime depends on the settings of placement. If we have high effort tool settings, then to achieve the target, tool normally takes long time where it increases the runtime.
• Few tool commands take more time to execute, hence runtime gets high. Similarly if the command takes less time to execute, then runtime of the design is low.
• As an example, sometimes tool does not get location to place a buffer during optimization which cause more time to identify the location and place the buffer.
• One more example, sometimes legalization takes lots of time to legalize the cells around that. It may be because of more cell congestion in the area and around.