Job Openings in VLSI

Cadence is hiring Interns for Bangalore location.

Educational Qualifications: BE/B.Tech or ME/M.Tech graduates.

Pre, Post Sale Support for University for Analog and Digital flow and PCB Products. Subsequently supporting commercial accounts for evaluation and data intensive technical activities.

Demo, Workshop, Seminar, Installations, Tool support, Delivery of trainings. Development of required documentation, test case and demo material and supporting the same through workshops. Supporting in Marketing events for University tradeshows and seminars.

Send your cv to –  sangram@cadence.com

Source: LinkedIn 

Intel India is conducting an interview for the post of SOC Design Engineer.

Job description:

Intel India is conducting an interview for the post of SOC Design Engineer.

Job duties and responsibilities:

• Oversees definition, design, verification, and documentation for SoC (System on a Chip) development. Determines architecture design, logic design, and system simulation.
• Defines module interfaces/formats for simulation.
• Performs Logic design for integration of cell libraries, functional units and subsystems into SoC full chip designs, and simulation for SoCs.
• Contributes to the development of multidimensional designs involving the layout of complex integrated circuits.
• Performs all aspects of the SoC design flow from high level design to synthesis, place and route, timing and power to create a design database that is ready for manufacturing.
• Analyzes equipment to establish operation infrastructure, conducts experimental tests, and evaluates results. May also review vendor capability to support development.

Qualifications required:

B.Tech/M.Tech in Electronics/VLSI/Microelectronics/Computer Science from reputed institute

Skills required:

• With strong VLSI design knowledge, circuit design knowledge, Synthesis, Place-Route optimization, backend electrical tool convergence including timing convergence and layout cleanup and scripting
• Experience in Custom and ASIC Physical Design, RV
• Electronic Design Automation tools, Design Compiler, IC Compiler/ICC Layout cleanup expertise DRCs, density, ipc, etc.
• Circuit design, TCL, Perl programming
• Strong analytical ability, problem solving and communication skills
• Ability to work independently and at various levels of abstraction.

Source: careersquare.in

Nvidia is looking for an ASIC Design Engineer – Hardware.

As a member of our ASIC backend/timing team, you’ll be working on product designs, focusing on such tasks as clocks, timing convergence, chip layout planning, design optimization and automation of work flows. Specifically you’ll be focusing on full chip layout planning (partitioning, planning clock distribution and other structures, methodology), full chip timing closure signoff (using tools such as Synopsys Primetime, Cadence Tempus etc.), design optimization, and gate-level design of high-speed logic. In this role you will also interface with architecture, rtl design, layout implementation, methodology and custom design teams to drive design implementation, timing analysis/closure all the way from micro-architecture to tape-out.

What You’ll Be Doing

• Develop and enhance timing analysis/signoff work flow from frontend (pre-layout) to backend (post-layout) at both chip and block level.
• Develop custom timing scripts using tcl/primetime for clock skew analysis, special circuits such as clock dividers, core logic <-> IO macros interfaces such as PCI-E, Frame-Buffer/Memory, HDMI, etc.
• Chip level Integration, physically partitioning and floor planning.
• Design optimization and timing convergence related tasks.
• Development of PD work flows.
  
  

Qualifications

• BS or MS or equivalent experience in Electrical Engineering or Computer Science.
• 2-5 years of relevant ASIC design experience ideally with a focus in timing.

Industry

Job Description

Oversees definition design verification and documentation for SoC System on a Chip development Determines architecture design logic design and system simulation Defines module interfacesformats for simulation Performs Logic design for integration of cell libraries functional units and subsystems into SoC full chip designs Register Transfer Level coding and simulation for SoCs Contributes to the development of multidimensional designs involving the layout of complex integrated circuits Performs all aspects of the SoC design flow from highlevel design to synthesis place and route timing and power to create a design database that is ready for manufacturing Analyzes equipment to establish operation infrastructure conducts experimental tests and evaluates results May also review vendor capability to support development

Qualifications

You must possess the below minimum qualifications to be initially considered for this position Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates Experience listed below would be obtained through a combination of your school workclassesresearch andor relevant previous job andor internship experiences

Minimum Qualifications

BS MS or PhD in Electrical Engineering Computer Engineering or Electrical Computer Engineering

Minimum 6 years experience with design principles and techniques in at least two of the following areas
ICC2Primetime
Process Design cooptimization for DensityPerformance improvements
RTL based power estimation optimization
Experience in CPUASIC design methodology and flow development particularly in the RLS Structural Design APR low power optimization domains
Programming skills in TCL Perl Python Java Script and shell scripting
Strong Unix skills
Good understanding of overall CPUSOC design cycle and requirements.

Roles And Responsibilities

Immediate requirement for Physical Design Engineer position.

Designation: Design Engineer

Experience: 4-10 years in setting up and run synthesis and P&R flow

Qualification: Masters in Electrical / Computer Engineering

Location: Jayanagar, Bangalore

If interested, please contact Nagalakshmi at 99454 55009 and nagalakshmi.r@ futuresandcareers.com

Essential Skills

• Expect to review the performance, power and area at each and every stage of implementation
• Expect to make changes in the floorplan or flow to improve PPA
• Run STA across multiple modes and corners
• Need to undergo some ECO cycles to meet performance targets
• Need to be conversant of power optimization techniques
• Run and clean gross issues at backend stage for:

• Static IR
• Dynamic IR (Vector based)
• Power/Signal EM
• Signoff DRC

Desired Skills and Experience

Floor planning, drc, routing, verification, ip, physical design, power optimization, optimization strategies, ir, sta, eco, pr, design, backend, synthesis, floorplan, performance, Clock Tree Synthesis, Physical Verification, Place, Route

The Opportunity

• B.E/B.Tech Electrical engineering with over 10 years or M.E/M.Tech Electrical engineering with over 8 years of  experience in digital design.

• Design/RTL experience in Verilog or SV is a must.

• Knowledge of scripting languages, such as PERL, Python.

• Knowledge in C++ programming .

• Verification experience in SV, UVM is an advantage.

• Knowledge of following are preferred / an advantage

 – Ethernet protocols (IEEE 802.3, 802.1Q, 802.1D, Routing protocols) preferred.

  – L2 / L3 / L4 Ethernet protocol knowledge

  – Encryption / Authentication algorithms and protocols

  – Precision Time Protocol (PTP, IEEE-1588)

• Good learning , problem solving interpersonal and communication skills.

• Ability to be a part of a team, working in cooperation

• Contact  
• Uday
• Mulya Technologies
• “Mining the knowledge Community”
• Email: muday_bhaskar@yahoo.com

Essential responsibilities:

• Partner with business teams and system engineering to develop mutually agreeable design specifications
• Provide high-level analysis on chip architecture trade-offs to ensure spec compliance and superior performance at a competitive cost
• Participate in design reviews and creating the necessary design and product documentation
• Supervise IC layouts to ensure a high-performance standard
• Characterize prototypes, developing test specifications and coordinating with test/product engineering to drive product releases
• Drive behavioral models

Qualifications and other requirements:

• Master of Science in Electrical Engineering, Electronics Technology, Electrical Engineering Technology, Electrical and Computer Engineering or related field
• Minimum Cumulative 3.0/4.0 GPA

Preferred qualifications:

• Demonstrated strong analytical and problem solving skills
• Strong verbal and written communication skills
• Ability to work in teams and collaborate effectively with people in different functions
• Strong time management skills that enable on-time project delivery
• Demonstrated ability to build strong, influential relationships
• Ability to work effectively in a fast-paced and rapidly changing environment
• Ability to take the initiative and drive for results.

Source: Careersquare.in 

Candidate would be required to work on various phases of SOC physical design activities of top level & block level – floor-planning, partitioning, placement, clock tree synthesis, route, physical verification (LVS/DRC/ERC/Antenna etc).

Should be able to meet congestion, timing and area metrics. Candidate would be required to do equivalence checks, STA, Crosstalk delay analysis ,noise analysis, power optimization. Should be able to implement timing and functional ECOs.

In this role, the Engineer will apply Broadcom’s proven design methodology and milestone flow to meet Broadcom’s rigorous criteria for achieving Right-first time silicon.

Candidate should have very good experience in layout activities of block and SoC level. Should be well experienced in floor-planning, partitioning, placement, clock tree synthesis, route and physical verification.

Should have excellent problem solving skill to help through congestion resolution and timing closure. Should have experience formal verification and timing analysis and ECO implementation.

Experience with tools such as Innovus/Encounter, ICC, Caliber, LEC, Primetime etc is highly desirable. Full chip tape out experience based on 7nm/16nm/28nm/40nm technologies is preferred.

Candidate should be able to work independently and guide other team members. Should be experienced in working in a global team and dynamic environment.

Should possess ability to learn and adapt to new tools and methodologies. Excellent communication skill is a must.

About the job

We are now looking for a Senior ASIC Design Engineer – Hardware.

As a member of our ASIC backend/timing team, you’ll be working on product designs, focusing on such tasks as clocks, timing convergence, chip layout planning, design optimization and automation of work flows. Specifically you’ll be focusing on full chip layout planning (partitioning, planning clock distribution and other structures, methodology), full chip timing closure signoff (using tools such as Synopsys Primetime, Cadence Tempus etc.), design optimization, and gate-level design of high-speed logic. In this role you will also interface with architecture, rtl design, layout implementation, methodology and custom design teams to drive design implementation, timing analysis/closure all the way from micro-architecture to tape-out.

What You’ll Be Doing

• Develop and enhance timing analysis/signoff work flow from frontend (pre-layout) to backend (post-layout) at both chip and block level.
• Chip level Integration, physically partitioning and floor planning.
• Develop custom timing scripts using tcl/primetime for clock skew analysis, special circuits such as clock dividers, core logic <-> IO macros interfaces such as PCI-E, Frame-Buffer/Memory, HDMI, etc.
• Design optimization and timing convergence related tasks.
• Development of PD work flows.

What We Need To See

• BS or MS in Electrical Engineering or Computer Science.
• 3+ years of relevant ASIC design experience ideally with a focus in timing.

NVIDIA is widely considered to be one of the technology world’s most desirable employers. We have some of the most brilliant and talented people on the planet working for us. If you’re creative and autonomous, we want to hear from you!

Source: LinkedIn 

Job description:

Synopsys is looking for engineering graduates/PG students to work as interns in the field of VLSI.

The role will be focused on VLSI design/Verification in one of the following areas related to connectivity protocols: USB/Ethernet/AMBA/MIPI/Memory Controllers.

Job duties and responsibilities:

Architecture exploration of the sub-blocks within one of these IPs to optimize for area, speed and power
VLSI Design & verification of these sub-blocks/exploration of latest features and standards.
Based on project assigned, the job would involve one or more of the following activities: Verilog/System Verilog/ Vera coding, Exposure to UVM methodology, working with EDA tools like Design Compiler for Synthesis, SpyGlass for Lint, VCS for simulation.

Qualifications and Experience required:

Must have completed Bachelors’ degree in Electronics/ Electrical Engineering.
Partial completion of MS/MTech preferable. (Electrical/Electronics/VLSI/MicroElectronics or allied specializations.)
Minimum 7.0 CGPA/ 70% in Bachelor’s in Engineering and 7.5 CGPA in Master’s till the current semester.
Need to be backed with consistently high academics in 10th std and 12th standard.

Preferred Experience:

Strong fundamentals in Digital electronics.
HDL Languages coding experience preferably in Verilog/Vera/System Verilog.

About the job

At AMD, we push the boundaries of what is possible. We believe in changing the world for the better by driving innovation in high-performance computing, graphics, and visualization technologies building blocks for gaming, immersive platforms, and the data center. Developing great technology takes more than talent it takes amazing people who understand collaboration, respect, and who will go the extra mile to achieve unthinkable results. It takes people who have the passion and desire to disrupt the status quo, push boundaries, deliver innovation, and change the world. If you have this type of passion, we invite you to take a look at the opportunities available to come join our team. Physical Design Engineer Description Top engineering skills just isn’t good enough for our Engineering teams, we need high creativity to solve some of the most vexing technical challenges that an engineer with face, anywhere. AMD is at the forefront of technology innovation of visual computing experience, our world evolves through the use of the products we create. AMD is the place where imagination becomes a reality. AMD does not do this alone we work alongside of the strongest engineering teams building the products that are changing how we live, work, and play. AMD?s customer-centric design approach of integrating our industry changing IP with customer-specific IP creates tailor-made solutions of APUs, Discrete GPUs, and flexible System-on-a-Chip (SoC) design methodology. Our teams deliver gaming consoles, hand held gaming devices, online gaming, home entertainment devices, high-performance computing, mobile computing and cloud computing product Requirements Physical design and implementation of digital circuit blocks, automated synthesis and place and route of digital blocks from RTL to GDS, and integration at the IP level for delivering high speed PHY IP Job role

MTS level -Physical Design Engineer 7 – 11 years of overall design experience, preferably with high performance IP designs Experience in automated synthesis and timing driven place and route of RTL blocks for high speed datapath and control logic applications Experience in automated design flows for clock tree synthesis, clock and power gating techniques, buffer/repeater insertion, scan stitching, design optimization for improved timing/power/area, and design cycle time reduction Experience in floorplanning, establishing design methodology, IP integration, checks for logic equivalence, physical/timing/electrical quality, and final signoff for large IP delivery Strong experience with tools for logic synthesis, place and route, timing analysis, and design checks for physical and electrical quality, familiarity with tools for schematics, layout, and circuit/logic simulation Versatility with scripts to automate design flow Strong communication skills, ability to multi-task across projects, and work with geographically spread out teams.

Source: LinkedIn 

About the job

Senior Physical Design Engineer Physical Design >> Senior Physical Design Engineer Post Senior Physical Design Engineer Required Experience 5 to 10 Years Location Delhi NCR, Bangalore, Hyderabad Openings 8-10 Education BE/B.Tech./MS/M.Tech.(Electronics or Electronics & Communication) Physical Design Engineer knowledge of PD Flow from netlist to GDS (Floorplanning, Synthesis, Power Planning, Placement & Optimization, CTS, Routing, ECO steps, Timing/SI) Good idea about OCV/MMMC and multi power designs (Level shifters, Isolation cells etc) Should have worked extensively on XTalk/SI/EM Knowledge about CTS, Clock tree methodology and clock skewing. Tool specific knowledge ICC, innovus, primetime, DC, Genus depending on the background Knowledge of DRC/LVS, IR Drop, Formal Verification and Synthesis. Job would require complete ownership from netlist to GDS for blocks. Should have worked on 28nm and lower technologies. Tools

ICC or Innovus for PnR , Encounter for FloorPlan , Redhawk for IR Drop, PT/PTSI , Calibre Activities

Physical design of Hard Macros/Partitions. gate-level- Netlist to GDS, technologies varying from 28nm to 7nm . PD activities involve Hard Macro floorplan/IR Drop/placement/CTS/Routing/Timing Optimization/Timing Closure/DRC/LVS.

Source: LinkedIn 

About the job

NXP Semiconductors N.V. (NASDAQ: NXPI) enables secure connections and infrastructure for a smarter world, advancing solutions that make lives easier, better, and safer. As the world leader in secure connectivity solutions for embedded applications, NXP is driving innovation in the automotive, industrial & IoT, mobile, and communication infrastructure markets. Built on more than 60 years of combined experience and expertise, the company has over 29,000 employees in more than 30 countries and posted revenue of $8.88 billion in 2019.

At NXP we impact day-to-day life for millions of people across the globe through our strategy of ‘Secure Connections for a Smarter World’. NXP works side-by-side with customers to develop cutting-edge products and solutions for Mobile, the Connected Car, Cyber Security, Portable & Wearable and the Internet of Things. Interested in knowing what the future will look like? It’s being created right here! We are passionate about winning in everything we do, we are especially passionate about delivering exceptional quality to our customers that goes beyond their expectations. This focus on exceptional quality combined with flawless execution and delivery is part of our DNA, it’s who we are. NXP is committed to finding and developing the best talent; talent that is not afraid of taking absolute personal responsibility; talent that will lead us to even greater levels of success. 

Source: LinkedIn  

About the job

Job Title Physical Design Engineer Job Code HWDIND230218_42 Job Description B.E/B.Tech/M.E/M.Tech in Electrical/Electronic/Computer Engineering 3 Years of Experience in Physical Design Verification Key skillsets

Floor-planning, power planning, Physical verification Tools

ICC, Primetime, StarRC, Redhawk good Physical verification experience who has limited hands-on in ICC and Primetime Also Acceptable Location Bangalore & Noida Package Highly competitive to match experience and capability.

Source: LinkedIn 

Responsible for and own all aspects of physical design and physical verification effort at a block level. Worked on Netlist to GDSII at block level for multiple tape-outs. Expertise in hierarchical partitioning of block-level subsystems. Hands on experience in implementing high performance cores, low power designs. Flat timing closure of hierarchical sub systems with signoff STA. Block level floor planning, power planning and IR drop analysis. Formal verification at various levels of design hierarchy with respect to golden RTL. Debugging and solution finding skills. Liaising with Team members and co-workers and Design team for delivery of the project and in finding solution. Develop, support and maintain physical design flows and methodologies. Desired Qualification University degree (B.Tech/ M.Tech) in Electronics/ Electrical Engineering or similar. Other candidates will be considered if they have relevant experience. 3-7 Years of engineering experience primarily focussing on Physical design. Strong interpersonal skills, excellent verbal and written communication skills. Self-motivated and willing to take up additional responsibilities to contribute to the teams success. Strong analytical, problem solving and debugging skills. Desirable Experience Experience in Power, Area with timing closure in parallel. Timing closure with Crosstalk and OCV (Advanced OCV), MMMC optimization. Working experience on various nodes viz. 65nm, 40nm, 28nm, 20nm, 14nm, 10nm. CTS and clock tree constraints creation for meeting clock specifications. Scan chain reordering / Scan Chain repartitioning. Timing ECO and Functional ECO implementation at Netlist stage. Good knowledge of standard cell libraries – circuit design and cell layout. Good understanding of STA, EM / IR and sign-off flows. High Performance Sub-Systems exposure. Understanding of Low Power Design (General Methodology, CPF, UPF). Physical Design Tool expertise viz. Cadence

Encounter / Innovus, Mentor Graphics Olympus, Synopsys

ICC, ICC2, Atoptech

Aprisa. TCL / PERL Scripting and creating quick procedures for solutions will be a plus. Top level implementation will be an added advantage.

Source: LinkedIn 

About the job

Senior Physical Design Engineer – IC 4 yearsBangalore Job Description Chip level floorplanning, partitioning, timing budget generation, powerplanning, top PnR, CTS, block integration and ECO generation. Block level implementation from netlist to GDS. Handling timing closure of high frequency blocks. Handling blocks of high instance counts 1M instance and above. Expertise in signoff closure Timing with SI and OCV, Power,IR and Physical Verification at both block and chip level. Understanding constraints and fixing techniques. Understanding SI prevention , fixing methodology and implementation. Proficient in layout edit techniques. Proficient in Synopsys ICC or Mentor Olympus and Atoptech tool set. Experience in Design Automation and UNIX system. Experience in Tcl/Tk, PERL is a plus.

Source: LinkedIn 

About the job

As part of our ongoing expansion, EnSilica need to strengthen our ASIC Implementation team. We are looking for bright candidates who have an enthusiasm and aptitude for working in this vital part of our business. The ideal candidate will have a strong academic record and 5-10 years experience in IC Physical Design (PD) using advanced digital ASIC development flows. You will have a solid track-record and be familiar with the challenges of implementing complex ASIC/SoC designs from RTL to tapeout-ready GDSII, preferably in process nodes down towards 5nm. The candidate should have customer and supplier-facing experience and excellent communication skills. Key responsibilities Take full-flow ownership of all stages of the digital RTL-to-GDSII implementation flow for complex block-level or full-chip ASIC designs. Work closely with our customers and other EnSilica teams to deliver projects on-time and to the required performance and quality levels. Setup, run, and maintain EDA tool flows, as needed, for each stage of the development flow. Follow EnSilicas ISO Quality Management System requirements for implementation, reviews, and reporting. Keep up to date with all aspects of advanced ASIC implementation methodology and best-practice to ensure that EnSilicas expertise and services are always current and appropriate for each customer project. Key Skills / Background 1st or 2.1 Electronics, Physics or relevant subject from a Tier 1 group University. 5-10 years experience in industry with a strong track record in Physical Design gained across several successful ASIC projects, and at process nodes down to ~7nm. Ability to quickly and efficiently solve problems, working both independently and with support from colleagues, our suppliers, and our customers where needed. Extensive hands-on experience with either Synopsys ICC1/2 or Cadence Innovus for block-level and/or full-chip physical design, preferably down to ~7nm FF. RTL synthesis using Design Compiler or Genus, including DFT/scan-insertion. Power-management implementation using UPF/CPF, including verification and power estimation. Timing closure and STA, including constraint development and verification. IR-drop/EM modelling, analysis and verification. Setup, use, and verification of RC extraction flows. Ability to setup, run, and debug DRC/LVS/ERC/DFM using at least one of the main EDA tool sets. Desirable skills Team leadership or technical management. Experience in foundry tapeout. ASIC package development and package/die co-design. Foundry, Packaging, and IP supplier engagement and management. Personal Skills Ability to take full ownership of a task from initial assignment through to successful completion and sign-off Quality-driven approach Excellent communication and interpersonal skills Self-motivated and adaptable Take ownership of problems Strong/Creative problem-solving skills Good team player.

Source: LinkedIn 

Sr.Physical Design Engineer

Key Responsibilities

• Must have specialized SoC implementation knowledge plus broader technical knowledge that facilitates more integrative thinking.
• Have responsibility for projects or processes of significant technical importance and for results in SoC implementation and related areas.
• Solve complex and non-recurring problems; is able to identify changes to existing processes/methods and partner with leads for development and implementation.
• Requires limited supervision and is evaluated according to project performance.
• Coaches and mentors less experienced staff; be a team player.

Required Skills

• SoC implementation expertise. Multi million gates integration.
• Physical Synthesis, Constraints validation.
• Floorplanning, Power planning.
• Clock Tree Synthesis (CTS).
• Scan Synthesis, Scan re-order.
• Static Timing analysis (STA).
• Analysis: IR, EM, Noise.
• Physical Verification.

Academic Credentials

Masters/Bachelors in VLSI/ECE/EE with relevant course work and project background with 5+ years of experience.

LOCATION:
Bangalore

Source: LinkedIn 

Job Description

Synthesis using DC. Floorplan, P&R. Physical verification (DRC, LVS). STA & Timing closure. LEC. Layout clean-up. Expert in Synthesis to Tape-out flow, including Layout, DFT, Timing Closure, and Chip Finishing. Ability to independently handle complex blocks to closure right from Synthesis. Worked on at least 2 end to end projects those spanned across entire life cycle of development. Ability to communicate with architecture, RTL design and other remote teams. Excellent verbal and written communication skills. Preferably experience in 20 nm, 14 nm flows. Performing a wide range of back-end activities, including synthesis of RTL, DFT insertion, power optimization, Floor-planning, PnR (Place and Route), Clock Tree Synthesis (CTS), Timing closure (STA), DRC, LVS, Antenna checks, IR drop (Red Hawk), multi voltage checks etc.. Participating in the development of a back-end ASIC design flow. Expertise in Synopsys suite (IC Compiler, Primetime, Design Compiler). Experience of UPF low power design through synthesis, place and route.

Other Details

Industry IT-Software/Software Services

Employement Type PERMANENT

Overview Location Bengaluru

Job Title

Physical Design Engineer

Source: LinkedIn 

Ability to handle the complete physical design and analysis of multiple designs independently Good understanding of the static timing analysis and experience of closing timing requirements on multiple designs Experience of closing power analysis (IR/EM), equivalency checks as well as low power checks Ability to run the physical verification as well as fix all the violations independently Exposure to the challenges in the physical design of chips targeted to 16nm/12nm technology Experience in writing scripts using standard scripting languages (TCL/Perl) Good communication skills 4 years of experience in physical design The job will involve working on multiple block level designs to close all the implementation, timing, power, and physical verification-related issues. The candidate is also expected to contribute to the chip level analysis runs and solve some of the complex issues in the design.

Source: LinkedIn 

Physical Design Engineer Roles & Responsibilities Take complete ownership for implementation of Block level designs Responsible for planning and execution of all aspects of Physical Design including Synthesis, Floor planning, Place and Route, Clock Tree Synthesis, Clock Distribution, IP integration, Extraction, Timing closure, Power and Signal Integrity Analysis, Physical Verification, DFM and Tape Out on 16nm nodes or below Must have participated in all stages of the design (floor planning, placement, CTS, routing, crosstalk avoidance, physical verification, IREM) Well versed with the Level timing closure (STA), Timing closure methodologies Role involves tasks in estimating power using industry standard tool,designing power grid , analyze power grid, doing static IR drop, dynamic IR drop Role involves analyzing DRC, LVS,ERC rule files for industry standard layout verification Working on very leading technology nodes 16nm, 14nm, 10nm, 7nm Well aware of place and route methodologies and hands on experience with timing convergence Good communication skill to negotiate with top level for convergence Experience 2 to 12 Years & above Education BE/ ME/ B.Tech/ M.Tech/ MS

Location: Bengaluru, Ahmedabad, Bhubaneswar, Noida, Hyderabad, Pune, Onsite in India

Job Description

The Physical Design Engineer should have hands on experience with layouts of memory building blocks like control, sense amplifiers, I/O Blocks, bit cell array and decoders etc in compiler context. He/She should have understanding of different memory compiler floorplan and top level integration.

The Physical Design Engineer (PDE) role actively bridges the gap between circuit engineering, design automation and mask design. The layout work required encompasses transistor/device cell level planning, layout, assembly and routing.

The PDE is expected to be productive and proficient in all aspects of layout – this includes Computer Aided Design (CAD) tool utilization (layout editing/verification/Design For Manufacturing (DFM)/quality), productivity macro usage, and solid understanding of all related methodologies and work flow models.

A PDE is expected to provide engineering judgment to key decision making and design trade-offs. Examples include IR drop analysis and resolution, Reliability Verification (RV. Electromigration, Self Heat) analysis and resolution, ECO assessment for feasibility, effort, risk, schedule analysis.

The PDE will work to continuously drive methodology definition and refinement for memory compilers. This entails working in conjunction with the Design Automation (DA) teams closely, and senior/principle design engineers to perform problem exploration, feasibility studies, analyze options, and establish; implement recommendations.

The PDE is able to independently assess; plan complex layout assignments and derive a realistic schedule to execute to and deliver on time.

Minimum Qualifications

Qualifications

• Bachelors of Science degree in EE, CS or a natural science
• 2+ years of experience with physical design including memory compilers
• Basic programming skills (UNIX shell script, Tcl, Perl)

Source: LinkedIn 

Physical Design Engineer Job Description The Physical Design Engineer should have hands on experience with layouts of memory building blocks like control, sense amplifiers, I/O Blocks, bit cell array and decoders etc in compiler context. He/She should have understanding of different memory compiler floorplan and top level integration. The Physical Design Engineer (PDE) role actively bridges the gap between circuit engineering, design automation and mask design. The layout work required encompasses transistor/device cell level planning, layout, assembly and routing. The PDE is expected to be productive and proficient in all aspects of layout – this includes Computer Aided Design (CAD) tool utilization (layout editing/verification/Design For Manufacturing (DFM)/quality), productivity macro usage, and solid understanding of all related methodologies and work flow models. A PDE is expected to provide engineering judgment to key decision making and design trade-offs. Examples include IR drop analysis and resolution, Reliability Verification (RV. Electromigration, Self Heat) analysis and resolution, ECO assessment for feasibility, effort, risk, schedule analysis. The PDE will work to continuously drive methodology definition and refinement for memory compilers. This entails working in conjunction with the Design Automation (DA) teams closely, and senior/principle design engineers to perform problem exploration, feasibility studies, analyze options, and establish; implement recommendations. The PDE is able to independently assess; plan complex layout assignments and derive a realistic schedule to execute to and deliver on time. Qualifications Minimum Qualifications

• Bachelors of Science degree in EE, CS or a natural science
• 2 years of experience with physical design including memory compilers
• Basic programming skills (UNIX shell script, Tcl, Perl) Inside this Business Group IP Engineering Group’s (IPG) vision Build IPs that power Intel’s leadership products and power our customer’s silicon. We want to attract & retain talent who get joy in building high quality IP and share our core belief that IP is fundamental to transforming Intel’s silicon design process. IPG’s guiding principles will be ensuring Quality (Zero Bugs), Customer Obsession (Delight our Customers) and structured Problem Solving. We are a fearless organization transforming IP development. Legal Disclaimer Intel prohibits discrimination based on race, color, religion, gender, national origin, age, disability, veteran status, marital status, pregnancy, gender expression or identity, sexual orientation or any other legally protected status.

Source: LinkedIn 

Job Overview:
Qualcomm is a company of inventors that unlocked 5G ushering in an age of rapid acceleration in connectivity and new possibilities that will transform industries, create jobs, and enrich lives. But this is just the beginning. It takes inventive minds with diverse skills, backgrounds, and cultures to transform 5Gs potential into world-changing technologies and products. This is the Invention Age – and this is where you come in.

The Responsibilities Of This Role Include

General Summary Plans, designs, and develops electronic systems, circuits, components, integrated circuitry, mechanical systems, equipment and packaging, optical systems, and/or DSP systems. Conducts simulations and analyses of designs. Develops emulation solutions. Evaluates, characterizes, and develops the manufacturing solution for leading-edge products in the most advanced processes. Interfaces with various cross-functional teams (e.g. Designers, Software/System Engineering, Architecture Development, Business Groups, Customers, Customer Engineering) to drive and incorporate the latest test solutions in the production program to improve the yield, test time, and quality. Evaluates reliability of materials, properties, and techniques used in production.

• Working independently with little supervision.
• Making decisions that are moderate in impact; errors may have financial impact or effect on projects, operations, or customer relationships; errors may require involvement beyond immediate work group to correct.
• Using verbal and written communication skills to convey complex and/or detailed information to multiple individuals/audiences with differing knowledge levels. May require strong negotiation and influence, communication to large groups or high-level constituents.
• Having a moderate amount of influence over key organizational decisions (e.g., is consulted by senior leadership to provide input on key decisions).
• Completing tasks that do not have defined steps; simultaneous use of multiple mental abilities is generally required to determine the best approach; mistakes may result in significant rework.
• Exercising substantial creativity to innovate new processes, procedures, or work products within guidelines or to achieve established objectives.
• Using deductive and inductive problem solving; multiple approaches may be taken/necessary to solve the problem; often information is missing or conflicting; advanced data analysis and interpretation skills are required.
• Occasionally participates in strategic planning within own area affecting immediate operations. The responsibilities of this role do not include:
• Financial accountability (e.g., does not involve budgeting responsibility).

Principal Duties & Responsibilities

• Develops complex features and components of hardware designs in line with proposals or roadmaps for complex products; advises less experienced engineers working together on common testing and design tasks.
• Applies advanced design rules and processes for electronic hardware, equipment, and/or integrated circuitry independently; has a basic understanding of other domains.
• Reads device specification sheets and interprets complex details required to design various hardware features; provides guidance to less experienced engineers working with spec sheets.
• Identifies advanced ways to optimize tests and/or hardware designs by evaluating device performance over a wide range of operating conditions and configurations.
• Evaluates complex design features to identify potential flaws (electrical, mechanical, hardware), compatibility issues, and/or compliance issues; advises less experienced engineers on design evaluations.
• Documents complex details about materials, components, chipsets, and functionality for a device while being mindful of potential compatibility, safety, and compliance issues; assists less experienced engineers in their documentation of these details.
• Troubleshoots advanced issues with product designs and finds solutions that are documented and shared with internal teams working on similar products.
• Provides essential technical input, support, and documentation for internal customers; advises less experienced engineers on how to provide support for clients.
• Acts as a tech lead on mid-sized to large projects and owns the outcome of the project.
• Manages project-related activities (e.g., meetings, documentation, deliverables) between their team and other teams working on the same or similar products, operating across locations and time zones; brings the project to conclusion.
• Utilizes deep understanding of Qualcomm products to evaluate and test hardware designs and identify unique components or functions that could potentially be filed for IP patents; shares these findings with their manager.
• Displays deep knowledge in a specific area; acquires advanced knowledge of industry trends, competitor products, and advances in various engineering fields from publically available information; shares knowledge with others on team and helps less experienced engineers understand and apply advanced concepts.
• Conducts specialized analyses (e.g., feasibility studies, signal integrity, power integrity, teardown analyses) and reviews analyses conducted; provides guidance and feedback to junior engineers in the execution and interpretation of these analyses. Additional responsibilities may also include: Develops design implementation, analysis, methodology, flows, and automation for development and validation of System on Chip, electronic parts, components, integrated circuitry, and packaging. Provides design solutions to evaluate, characterize and develop the design implementation solution for leading-edge products in the most advanced processes. Interfaces with various cross functional teams (RF, Analog and Digital IC designers, Software, System Engineering, Test Engineers, Customer Engineering, and Operations) to drive and incorporate the latest design solutions in the production program to improve yield, productivity, and quality.

IT Core Competencies N/A

Required Competencies (All competencies below are required upon entry)

• Analytical Skills – The ability to collect information and identify fundamental patterns/trends in data. This includes the ability to gather, integrate, and interpret information from several sources.
• Building Trusting Relationships – The ability to build trusting, collaborative relationships and rapport with different types of people and businesses. This includes delivering on commitments and maintaining confidential information, as well as being approachable, showing interest in the other person, and relating well to people regardless of personality or background.
• Communication – The ability to convey information clearly and accurately, as well as choosing the most effective method of delivery (e.g., email, phone, face-to-face). This includes using a technically sound communication style both verbally and in writing.
• Creating the New and Different – The ability to be creative. This includes the ability to produce breakthrough ideas, being a visionary, managing innovation, seeing multiple futures, having broad interests and knowledge, and gaining support in order to translate new ideas into solutions. This also includes the ability to plan and implement unconventional ideas and speculate about alternative futures without all of the data.
• Decision Making – The ability to make quick, accurate decisions. This includes the ability to weigh alternatives and take into account the impact of the decisions on people, equipment, or other resources.
• Documentation – The ability to appropriately document software and/or hardware specifications and processes to promote knowledge transfer to other engineers.
• Getting Work Done – The ability to be organized, resourceful, and planful. This includes the ability to leverage multiple resources to get things done and lay out tasks in sufficient detail. This also includes the ability to get things done with fewer resources and in less time, work on multiple tasks at once without losing track, and foresee and plan around obstacles.
• Hardware Design – Knowledge of and the ability to understand advanced or complex hardware design elements in order to carry out designs, upgrades, and technology roadmaps.
• Hardware Infrastructure – The ability to implement and integrate IT hardware for use in business environments and assist in designing its main features according to business needs. This includes the ability to track and report operational problems. This also includes the ability to compare IT hardware across one’s own organization and its competitors.
• Mentoring and Coaching – The ability to develop, coach, and mentor associates. This includes the ability to provide development experiences and network opportunities, advise, and teach to prepare associates for effective job performance.
• Project Management – The ability to use organizational skills for purposes of planning and decision-making. This includes developing and communicating objectives, timelines, assignments, and goals. This also includes the ability to scope projects, orchestrate multiple activities at once, and use resources efficiently across functional areas within the enterprise.

Additional Competencies N/A

Minimum Qualifications

• Bachelor’s degree in Engineering, Information Systems, Computer Science, or related field.
• 5+ years Hardware Engineering experience or related work experience.

Preferred Qualifications

• Master’s Degree in Engineering, Information Systems, Computer Science or related field.
• 8+ years Hardware Engineering experience or related work experience.
• 2+ years experience with circuit design (e.g., digital, analog, RF).
• 2+ years experience utilizing schematic capture and circuit simulation software.
• 2+ years experience with hardware design and measurement instruments such as oscilloscopes, spectrum analyzers, RF tools, etc.
• 1+ years in a technical leadership role with or without direct reports.

Physical Requirements

• Frequently transports between offices, buildings, and campuses up to ½ mile.
• Frequently transports and installs equipment up to 5 lbs.
• Performs required tasks at various heights (e.g., standing or sitting).
• Monitors and utilizes computers and test equipment for more than 6 hours a day.
• Continuous communication which includes the comprehension of information with colleagues, customers, and vendors both in person and remotely.

Applicants: If you need an accommodation, during the application/hiring process, you may request an accommodation by sending email to accommodationsupport

To all Staffing and Recruiting Agencies:Our Careers Site is only for individuals seeking a job at Qualcomm. Staffing and recruiting agencies and individuals being represented by an agency are not authorized to use this site or to submit profiles, applications or resumes, and any such submissions will be considered unsolicited. Qualcomm does not accept unsolicited resumes or applications from agencies. Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications.

Source: LinkedIn

What you’ll do

• Design, and implement solutions using knowledge of timing, floor-planning, high speed design techniques, and formal verification techniques.
• Apply semi-custom, and ASIC-methodologies, as required, to run, synthesis, placement, CTS, routing, and complete other physical design tasks to make the block ready for sign-off.
• Use EDA tool-based programming and scripting techniques to automate and improve throughput and quality.
• Implement lower-geometry designs using CMOS-7nm rules, device characteristics to implement data-paths, and large physical blocks.
• Use state-of-the-art macro-compilers, design-cell libraries to provide appropriate design libraries to the processor design team.

What you’ll bring

• Minimum 6 years of relevant experience in VLSI design, high-speed microprocessor design
• Hands on experience in floor planning, place & route, power and clock distribution, pin placement and timing constraints generation
• Timing convergence using high speed design techniques
• Physical design of high frequency chips with emphasis on successful timing closure
• Excellent understanding of geometry/ process/ device technology implications on physical design. 16nm and 7nm experience is required
• Good understanding of static timing analysis (STA), EM/IR and sign-off flow
• Experience in physical design verification
• Good programming/scripting skills: Tcl, python, expect, shell

Education

• BS/MS in Electrical Engineering

Source – LinkedIn 

Proven experience in constraints (Func/Test) handling, block and top level static timing analysis, ECO generation at top level, handshaking with blocks for timing/functional ECO implementation, good exposure in Synthesis for block and top level. . Experience in Power Analysis and fixing is a good add-on experience.

Desired Skills and Experience

Engineering

Source: LinkedIn

About the job

Looking for Physical Design engineer

Experience range : 4 – 20 years

Location : Bangalore

Job Description :

Responsibilities

Complex Subsystem/ subchip/ partition/tile GLN2GDS delivery ownership
Resolve congestion, timing, power, runtime related issues in Physical design
Coordination with chip level build activities, fully resolves schedule dependencies from his/her ownership
An individual contributor, come up with requirements to execute on R&R early in the design cycle

Requirements

A minimum of 6-12 years of exclusive physical design experience
Specialist in at least one EDA tool, but is tool/ methodology/ flow agnostic with great functional domain knowledge,
Extreme proficiency in at least one programming language like TCL/ PERL
Delivered multi-Gigahertz, multi-million subsystem/ subchip/ partitions, as hands-on individual contributor for GLN2GDS.
Works on extremely ambitious, results-oriented schedule
Excellent data driven reasoning, quick learner & analytical skills on job
Bachelors of Engineering/ Master of Technology in E&C/ Electrical/ Computer Science.

Please send in your updated resume to nagavenu.vidiyala@skandysys.com

Source: LinkedIn

About the job

THE PERSON

The successful candidate for this position will interact closely with key AMD technical experts to ensure the best possible performance and results on AMD platforms. This is a great opportunity to work as a part of highly regarded team to deliver leading edge solutions.

KEY RESPONSIBILITIES

This position will be responsible for implementation of digital circuit blocks, automated synthesis and place and route of digital blocks from RTL to GDS, and integration at the IP level for delivering high speed PHY IPcore

PREFERRED EXPERIENCE

7 – 11 years of overall design experience, preferably with high performance IP designs Experience in automated synthesis and timing driven place and route of RTL blocks for high speed datapath and control logic applications Experience in automated design flows for clock tree synthesis, clock and power gating techniques, buffer/repeater insertion, scan stitching, design optimization for improved timing/power/area, and design cycle time reduction Experience in floorplanning, establishing design methodology, IP integration, checks for logic equivalence, physical/timing/electrical quality, and final signoff for large IP delivery Strong experience with tools for logic synthesis, place and route, timing analysis, and design checks for physical and electrical quality, familiarity with tools for schematics, layout, and circuit/logic simulation Versatility with scripts to automate design flow Strong communication skills, ability to multi-task across projects, and work with geographically spread out teams.

Source: LinkedIn

About the job

Who Are We

POP Implementation team part of Physical Design Group(PDG) at Arm Bangalore.

POP team is an experience to see the bigger picture of technical, business and problem solving aspects through the journey of building Arm CPU, GPU, NPU and Interconnect implementations. So what are the aspects we touch upon a daily basis?

• Physical implementation of Arm’s latest CPU, GPU, NPU and Interconnect IP.
• Exposure to advanced and mainstream technology nodes(3nm/5nm/7nm/12nm/22nm) being driven by multiple foundries.
• Path-finding for Performance, Power and Area(PPA) metrics using varied recipes along with backend closure that’s representative of a tape-out.
• Implementation flow and PPA tuning across multiple vendor based EDA flows in parallel.
• Collaborating with Arm sales, marketing and end customers to refine the physical IP and implementation products.
• Contribute in brainstorming ideas, approaches and recipes on all products being designed in the team.
• Learn the intricacies of supporting products across different market segments like Client, Infrastructure, Automotive, IOT and Machine Learning.
• Celebrate with the team to rejuvenate the mind and spirit for accomplishing greater things in future.
  
  

What You’ll Be Doing

• You will be expected to build implementations of Arm CPU/GPU class designs using Arm’s optimized physical IP.
• You will need to setup RTL, integrate memory models, create floorplans, setup synthesis / P&R flow and complete backend closure.
• The primary objective would be to optimize performance, power and area as required by the Arm IP and the associated market segment.
• In terms of backend closure, you will need to take the design through STA, EM, IR drop, signoff DRC and other types of verification steps.
• You will also need to work on lighter aspects related to DFT(scan insertion, compression and ATPG) and setup Gate-level simulations to report power.
• Your daily job will demand a lot of handshaking with physical IP teams who are responsible for “optimized” standard cell and memories.
• You will also need to work with EDA partners in an independent manner to create and deploy recipes related to EDA tools.
• You will see exposure to sales, marketing and licensing teams at Arm.
• You will also be interacting with end customers directly to help them in usage of POP IP through the complete customer product tape-out cycle.
• You will be expected to drive a lot of knowledge sharing sessions with wider audiences.
  
  

Qualification & Experience

• BE/BTECH/MTECH with 4 to 5 years of minimum experience in Physical Design domain.
• A star that believes in making the whole constellation brighter rather than shining all alone. We are only about “We” and not “I”.
• Values communication as a key medium to nurture learning, builds trust with others and solves complex problems with dependencies.
• Strong understanding in the RTL2GDSII flow for leading or mainstream process technologies.
• Good understanding of the concepts related to synthesis, place & route, CTS, timing convergence, IR/EM checks and signoff DRC/LVS closure.
• Any implementation experience on Arm CPU and GPU IP designs would be very useful.
• Expertise on optimizing for cost functions like performance, power and/or area is like gold dust.
• High-level know-how related to foundation IPs like standard cells and memories fits well with our work.
• Working experience with tools like DC/Genus, ICC2/Innovus,Primetime/Tempus etc used in the RTL2GDSII implementation.
• Good automation skills in PERL, TCL and EDA tool specific scripting can be impactful.
  
  

Arm core beliefs At Arm, we are guided by our core beliefs that reflect our unique culture and guide our decisions, defining how we work together to defy ordinary and shape extraordinary

We not I

• Take daily responsibility to make the Global Arm community thrive
• No individual owns the right answer. Brilliance is collective
• Information is crucial, share it
• Realise that we win when we collaborate — and that everyone misses out when we don’t (what does collaborate)

Passion for progress

• Our differences are our strength. Widen and mix up the pool of people you connect with
• Difficult things can take unexpected directions. Stick with it
• Make feedback positive and expansive, not negative and narrow
• The essence of progress is that it can’t stop. Grow with it and own your own progress

Be your brilliant self

• Be quirky not egocentric
• Recognise the power in saying ‘I don’t know’
• Make trust our default position
• Hold strong opinions lightly

With offices around the world, Arm is a diverse organisation of dedicated, innovative and highly talented professionals. By enabling a vibrant, inclusive, meritocratic, and open workplace, where all our people can grow and succeed, we encourage our people to share their unique contributions to Arm’s success in the global marketplace.

Source: LinkedIn 

Hands on knowledge of complete ASIC physical design – floor planning to design closure Been involved in a few challenging designs and tapeout Been involved and understands ECO flows Hands on knowledge of design fixes for timing closure, SI, EM-IR, DRC/ LVS closure Good knowledge of DSM and DFM issues Basic knowledge of DFT concepts (Scan, BIST, JTAG etc.) Familiarity with different types of libraries used in the physical design flow Hands on knowledge of working on Cadence/ Synopsys/ Magma toolset Worked on 65nm/ 45nm/28nm technology nodes Basic knowledge of STA using PT/ PTSI Good conceptual knowledge of OCV, MCMM analysis, EM-IR drop, low power methodologies

Scripting skills: Unix, Shell scripting (CSH/ BASH etc.), MAKE, AWK, PERL/ TCL is a must – Good team player and ability to work with stakeholders like RTL team, DFT team and verification team Worked on complete SoC physical design Domain knowledge of protocols like USB, DDR etc. Good knowledge of different types of IOs Basic knowledge CMOS and layout Worked on designs involving power management using different voltage domains Good knowledge of STA

Toolset : Cadence (FE/ VSPE/ QRC/ ETS) or Synopsys (ICC) or Magma, Caliber/ Hercules, StarRCXT/ QRC. 

Source: LinkedIn

Educational/Experience Requirements: BSEE with 6+ years of experience in ASIC design experience in all aspects of physical design. Excellent verbal and written communication skills are required. Must possess at last five years of recent hands on experience in the place & route domain (direct IC Compiler and or IC Compiler II is preferred, or competing place and route tools).

Well-qualified candidates will have the following experiences and skills:

(1) Must have hands-on experience with physical design of complex, high performance processor subsystems and/or ASICs

(2) Must demonstrate knowledge of the Synopsys tools, flows and methodologies required to execute physical design projects

(3) Will have proven experience contributing to 2+ project tape-outs

(4) Must possess collaborative teamwork experience and the aptitude and motivation to work with other internal and customer groups.

Source: LinkedIn

Physical Design Engineer Position : Physical Design Engineer

Experience : 2 – 7 Years

Education : B.Tech/ BE/ ME/ M.Tech

Job Location : Bangalore / Chennai / Hyderabad / Noida Desired

Skills : Include all aspects of physical design including synthesis, floor planning, place and route, Clock Tree Synthesis, Clock Distribution, extraction, Timing closure, Power and Signal Integrity Analysis, Physical Verification, DFM and Tape Out. Should be able to interface with Front End Design team to resolve Design Issues

Responsibilities: Must possess hands on experience in P&R; from RTL to GDS including timing closure and Physical verification. Design experience in all aspects of physical design. Proficient and powerful user of Synopsys DC, Cadence SOC Encounter. Experience in Mentor Calibre tools to run Physical verification Experience in Apache to run EM IR- analysis is a Plus. Experience in Tcl/ Tk, PERL, Makefile is a Plus Excellent verbal and written communication skill is required. Excellent interpersonal and analytical skills with an ability to work independently and within a team are required. Highly motivated, excellent team player, and customer oriented.

Source: LinkedIn 

The Role

AMD is looking for a an MTS Physical Design Engineer with experience in implementation of digital circuit blocks, automated synthesis and place and route of digital blocks from RTL to GDS, and integration at the IP level for delivering high speed PHY IPcore

The Person

The successful candidate for this position will interact closely with key AMD technical experts to ensure the best possible performance and results on AMD platforms. This is a great opportunity to work as a part of highly regarded team to deliver leading edge solutions.

Key Responsibilities

This position will be responsible for implementation of digital circuit blocks, automated synthesis and place and route of digital blocks from RTL to GDS, and integration at the IP level for delivering high speed PHY IPcore

Preferred Experience

7 – 11 years of overall design experience, preferably with high performance IP designs
Experience in automated synthesis and timing driven place and route of RTL blocks for high speed datapath and control logic applications
Experience in automated design flows for clock tree synthesis, clock and power gating techniques, buffer/repeater insertion, scan stitching, design optimization for improved timing/power/area, and design cycle time reduction
Experience in floorplanning, establishing design methodology, IP integration, checks for logic equivalence, physical/timing/electrical quality, and final signoff for large IP delivery
Strong experience with tools for logic synthesis, place and route, timing analysis, and design checks for physical and electrical quality, familiarity with tools for schematics, layout, and circuit/logic simulation
Versatility with scripts to automate design flow
Strong communication skills, ability to multi-task across projects, and work with geographically spread out teams

Academic Credentials:

Qualification: Bachelors or Masters in Electronics /Electronics Engineering

Source: LinkedIn 

Role

In this role as a Principal Physical Design Engineer in Non-Volatile Engineering Group, you will be responsible for crafting next generation ASIC products for on most recent technology nodes.

Responsibilities

Complex Subsystem/subchip/partition/tile RTL2GDS delivery
Chip build/integration – Floorplan, Partitioning, Pin placement, Budgeting, Power Plan, Bump plan & routing, Package co-design, Early analysis.
PPAS early data analysis, improve & drive PPAS improvements
Static timing analysis, constraint analysis, coverage and modifications
Chip level CTS build – analysis – refine, and do suggest early on re-architecture of reset and clock schemes for better PPAS
Chip level Signal integrity and Power integrity checks, analysis & fix
Full chip Physical verification
Coordination with subsystem/subchip/partition/tile owners
An individual contributor, knows requirements to execute his/her responsibilities and seamlessly drives needed coordination among technical team members to constantly achieve better PPAS

Requirements

A minimum of 13-19 years of exclusive physical design experience
Specialist in at least one EDA tool, but is tool/methodology/flow agnostic with great functional domain knowledge, with extreme profiency in at least one programming language like TCL/PERL
Has done at least one multi-partition/multi-million gate System on Chip / Test chip as top level hands-on lead. OR,
Delivered multi-Gigahertz, multi-million subsystem/subchip/partitions, as hands-on individual contributor for RTL2GDS.
Leads by example, works on ambitious, results-oriented schedule & does data driven, flawless synchronized decision making
Proficient in timing constraints, physical constraints, floorplanning, PG planning, Timing Modes & Margins
Knowledge of abstract timing/physical models, creation of.
Excellent analytical skills
Specialist in collaborating in a team of multi-functional, geographically distributed members with highly diverse skill levels.
Bachelors of Engineering/Master of Technology in E&C/Electrical/Computer Science.

Preferred Skills:

Strong verbal communication skills
Analog/MS/RF layout/design experience
RTL coding/verification experience
Test insertion experience
ESD – Need, Implement, Check mechanism – exposure to
Package design, PCB design experience
Post-Silicon support experience

Contact: Uday Bhaskar

Mulya Technologies

“Mining the Knowledge Community”

Email id : muday_bhaskar@yahoo.com

Source: LinkedIn 

Title : Sr. Physical Design Engineer

Location : Bangalore

Duration : Full time

Looking for at least 5+ yrs of experience.

Bachelors or Masters degree in Electrical, Electronics or Computer Engineering with 5-12 years of relevant industry experience.
Minimum 5 years’ experience with design principles and techniques in SoC and/or VLSI back-end design and/or integration.
Strong planning, and problem-solving skills
Experience hands-on execution (synthesis, place & route, timing analysis, and SD verification tools).
Knowledge of logic design principles along with timing and power implications
Understanding of low power micro architecture and implementation techniques
Familiarity with high performance architecture
Experience with scripting in Python, Perl and/or TCL
Experience in 16/14/10/7nm a process is a must
Demonstrate ability to work with RTL and DFT teams.

Source: LinkedIn 

About the job

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.
Familiarity with Shell & perl scripting. SKILL know-how will be big plus.
Knowledge of VLSI, analog design flow, and design & verification tools.

Educational Qualification:

BE/B.Tech/ME/M.Tech

Seniority Level
Internship

Industry

Information Technology & Services, Computer Software, Semiconductors

Employment Type

Full-time

Job Functions

Sales Business, Development

Source: LinkedIn

Micron Technology Hiring Freshers for Analog Design Engineer

Qualifications: (B.E./B.Tech) in Electronics

Job Role: Analog Design Engineer

Industry Type: Electrical & Electronic Manufacturing

Functional Area: Semiconductors

Minimum Qualifications:
– A high level of self-motivation.
– Proficiency performing analog and mixed signal simulations using standard industry simulators.
– Knowledge of circuit verification and optimization, including layout planning, verification and parasitic extractions of the circuits.
– Familiarity with Cadence design, LVS/DRC tools (a plus).
– Good fundamentals in semiconductor and device physics.
– Strong circuit debugging and problem-solving skills.
– Good communication and teamwork skills.
– BSEE/MSEE degree required. MSEE preferred.

Interested candidates apply through the below link. Apply before the link expires.
https://lnkd.in/g4PsWky

Sr. Physical Design Engineer – Block Execution
Company Name: Wafer Space Company Location Bengaluru, Karnataka, India

Able to take up ownership of blocks independently (RTL2GDSII; 16nm and lower technology nodes)

• Interface with RTL designers and solve structural inefficiencies if any
• Functional & DFT Constraint development exposure
• Need to be able to make smart decisions like optimal standard cell selections based on PPA targets
• Need to come up with strategies to control congestion through understanding of specific block level architectural challenges
• Need to come up with strategies to fix RC inefficiencies built into layout and achieve timing closure
• Should be able to construct clocks on multi-clock, synchronous and asynchronous clock domain partitions
• Should be good in STA analysis
• Should have owned DRC/LVS/ANT clean ups at block level
• Implementation experience on IR/IVD/EM analysis & fix
• Should be good in Innovus, Tempus & Genus
• Low Power Implementation experience will be a big plus
• Relevant Experience: 4 years+

Seniority Level
Mid-Senior level

Industry
Semiconductors

Employment Type
Full-time

Job Functions
Engineering Information Technology

SOURCE: LinkedIn

Responsibilities

You will be responsible for the path finding, design , Si validation and support of primitive copy-exact analog foundational IP’s such as

Analog transistors, resistors, capacitors, ESD diodes, Power clamps and thermal sensing devices.

Your Responsibilities Include

Define copy-exact foundational IP in collaboration with analog and I/O designers in product groups and AD.
Work with process/device/Q&R stake holders as part of DTCO to co-optimize design and process modeling/rules.
Design schematic/layout and take them through all PV/RV/ESD characterization flows.
Ensure industry standard TFM and EDA support is enabled for all collateral.
Implement test structures in Si to characterize performance metrics and Perform on-going updates based on latest sil2sim learnings.

Qualifications

You must possess the below minimum qualifications to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates. Experience listed below would be obtained through a combination of your school work/classes/research and/or relevant previous job and/or internship experiences.

Minimum Requirements

• Academic Qualification: BE/B.Tech or ME/M.Tech in Electronics/VLSI Design
• Minimum 7+ years of experience with strong VLSI design knowledge, circuit design knowledge, semiconductor device physics, Custom/Analog Layout/Mixed Signal layout design and scripting.
• Good knowledge of analog circuit design , layout methodology and interaction with EDA tool/flows.
Coding skills in skill, tcl and other programming language to improve work efficiency is a bonus.

Seniority Level
Entry level

Industry
Electrical & Electronic Manufacturing, Information Technology & Services Computer Software

Employment Type
Full-time

Job Functions
Engineering, Information Technology

Source – LinkedIn 

Key Qualifications

The role involves developing and working on verification of high speed PHYs and Serdes. Additionally you will be involved in:
BE/BTech +4 years of relevant experience / MTech +3 years of relevant experience in Electrical Engineering or other relevant field of study.
Verification plan development and its review
Verification environment development
Verification using internal or 3rd party VIP for the protocol of interest
Debug of simulations, including those of real signals modeled using SV for analog
RTL, GLS & Co-simulations & coverage closure
Participate in technical reviews and contribute actively
Follow and improve development process ensuring high quality output.

Preferred Experience

Knowledge of protocols like 25G/50G/100G Ethernet, PON, other networking protocols
Hands on experience in creating Verification Environment from Functional Specifications
Test planning, Coverage and Assertion planning
Hands on experience with System Verilog, mythologies like UVM, simulation and debug tools.
Experience with Version Control tools like Perforce/SVN.
Knowledge of Perl/Shell scripts
Inclusion and Diversity are important to us. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, gender identity, age, military veteran status, or disability.

Seniority Level
Entry level

Industry
Semiconductors, Computer Software, Computer Hardware

Employment Type
Full-time

Job Functions
Design, Consulting, Engineering

Source – LinkedIn 

Required skills and Qualification

B.Tech/M.Tech in Electrical or Electronics or Computer Science Engineering.
4+ years of experience in Physical Design.
In-Depth experience in Physical Design Implementation & Signoff at block level at 16/7nm technology nodes.
Good exposure in Floorplanning, CTS, STA, Physical Verification.
Basic understanding of timing constraints.
Good exposure to ICC2/Innovus/Calibre/Formality/LEC toolset.
Well versed in automation skills using shell/TCL/Perl/python.

Seniority Level
Mid-Senior level

Industry
Semiconductors

Employment Type
Full-time

Job Functions
Engineering

Source – LinkedIn 

Senior Physical Design Engineer
CompanyName: NVIDIA Company Location Bangalore, IN

NVIDIA is seeking passionate, highly motivated, and creative senior design engineers to be part of a team working on industry-leading GPUs and SOCs. This position offers the opportunity to have real impact in a dynamic, technology-focused company impacting product lines ranging from consumer graphics to self-driving cars and the growing field of artificial intelligence. We have crafted a team of exceptional people stretching around the globe, whose mission is to push the frontiers of what is possible today and define the platform for the future of computing.

What You’ll Be Doing?

In this position, You will expected to lead all block/chip level PD activities.
PD activities includes floor plans, abstract view generation, RC extraction, PNR, STA, EM,IR DROP, DRCs & schematic to layout verification. Work in collaboration with design team for addressing design challenges.
Help team members in debugging tool/design related issues.
Constantly look for improvement in RTL2GDS flow to improve PPA. Troubleshoots a wide variety up to and including difficult design issues and applied proactive intervention
Responsible for all aspects of physical design and implementation of GPU and other ASICs targeted at the desktop, laptop, workstation, and mobile markets.

What They Need To See?

BE/BTECH/MTECH with 3+ years of experience in Physical Design.
Strong understanding in the RTL2GDSII flow or design implementation in leading process technologies. Good understanding of the RTL2GDSII concepts related to synthesis, place & route, CTS, timing convergence, layout closure.
Expertise on high frequency design methodologies. Good knowledge and experience in Block-level and Full-chip Floor-planning and Physical verification. Working experience with tools like ICC2/Innovus, Primetime/Tempus etc used in the RTL2GDSII implementation.
Strong knowledge and experience in standard place and route flows ICC2/Synopsys and Innovus/Cadence flows preferred. Well versed with timing constraints, STA and timing closure.
Good automation skills in PERL, TCL, tool specific scripting on one of the industry leading Place & Route tools.
Ability to multi-task and flexibility to work in global environment.
Good communication skills and strong motivation, Strong analytical & Problem solving skills. Proficiency using Perl, Tcl, Make scripting is preferred.

Industry
Computer Hardware, Computer Software, Consumer Electronics

Employment Type
Full-time

Job Functions
Engineering

SOURCE: LinkedIn

Job Title: ASIC RTL Design

Preferred Qualifications:

– Strong Domain Knowledge on RTL Design , implementation and integration

– Experience with RTL coding using Verilog/VHDL/System Verilog

– Experience in micro-architecting & designing cores and ASICs

– Familiar with the Synthesis, Formal Verification, Linting, CDC, Low Power , UPFs, etc

– Simulation debugging with Verdi & log file.

– Exposure in scripting

– Good team player. Need to interact with the verification engineers proactively

– Ability to debug and solve issues independently

Educational Qualification:

– Bachelor’s degree /Master’s Degree in Engineering, Information Systems, Computer Science, or related field.

Experience: 3 to 6 Years

Seniority Level
Mid-Senior level

Industry
Semiconductors

Employment Type
Full-time

Job Functions
Engineering, Information Technology

Source – LinkedIn

Moschip provides once in a lifetime opportunity to work on cutting-edge technology and build a great career in the semiconductor industry.Physical Design JD:He/She should be able to do top-level floor planning, PG Planning, partitioning,placement, scan-chain-reordering, clock tree synthesis, timing optimization, SI aware routing, timing analysis/closure and ECO tasks (timing and functional ECOs), SI closure, design rule checks (DRC), and Logical vs. Schematic (LVS) checks, Antenna checks. He/She should have worked on 65nm or lower node designs with adv low power techniques such as Voltage Islands, Power Gating and substrate-bias.- Provide technical guidance, mentoring to physical design engrs.- Interface with front-end ASIC teams to resolve issues.- Low Power Design – Voltage Islands, Power Gating, Substrate-bias techniques.- Timing closure on DDR2/DDR3/PCIE interfaces.- Excellent communication skills.- Strong Back ground of ASIC Physical Design: Floor planning, P&R, extraction, IR Drop Analysis, Timing and Signal Integrity closure.- Extensive experience and detailed knowledge in Cadence or Synopsys or Magma physical Design Tools.- Expertise in scripting languages such as PERL, TCL.- Strong Physical Verification skill set.- Static Timing Analysis in Primetime or Primetime-SI.- Good written and oral communication skills. Ability to clearly document plans.- Ability to interface with different teams and prioritize work based on project needs. (ref:hirist.com)

Seniority Level
Entry level

Industry
Computer Hardware, Computer Networking, Semiconductors

Employment Type
Full-time

Job Functions
Engineering, Information Technology

Source : LinkedIn 

 Responsibilities:

As a Digital Physical design engineer in the team, you will be working on taking the digital design systems from RTL to physical design for the USB C/PD products.

Take the ARM based digital systems to
Focus on die area consumed and look for optimal realization of the system
Ensure that all the process flow constraints are met at the system level and work with the relevant engineers to get the violations understood and resolved

Minimum Qualifications: 

Bachelor or Master’s degree in Electrical engineering.
3+ years design experience including successful PG of 1 or more devices
Knowledge of Verilog, and knowledge of synthesizable constructs of system Verilog
Expertise with tools utilized in all phases of ASIC development, including Verilog simulation, Lint, CDC, synthesis, and timing analysis
Understanding of backend flows like place and route and timing closure.
Experience in physical design with demonstrated ability in area optimization and constraint closures

Preferred Skills/ Experience:

Experienced with physical design on a ARM based digital/mixed signal devices
Effective communication skills to interact with all stakeholders.
Ability to communicate effectively, and accommodate requirements of team members in other disciplines, including analog hardware, validation & system engineering. 

Seniority Level
Mid-Senior level

Industry
Semiconductors

Employment Type
Full-time

Job Functions
Engineering

Source : LinkedIn 

Minimum Qualifications
Bachelor’s degree in Engineering, Information Systems, Computer Science, or related field.
5+ years Hardware Engineering experience or related work experience.

Preferred Qualifications
Master’s Degree in Engineering, Information Systems, Computer Science or related field.
8+ years Hardware Engineering experience or related work experience.
2+ years experience with circuit design (e.g., digital, analog, RF).
2+ years experience utilizing schematic capture and circuit simulation software.
2+ years experience with hardware design and measurement instruments such as oscilloscopes, spectrum analyzers, RF tools, etc.
1+ years in a technical leadership role with or without direct reports.

Physical Requirements
Frequently transports between offices, buildings, and campuses up to ½ mile.
Frequently transports and installs equipment up to 5 lbs.
Performs required tasks at various heights (e.g., standing or sitting).
Monitors and utilizes computers and test equipment for more than 6 hours a day.
Continuous communication which includes the comprehension of information with colleagues, customers, and vendors both in person and remotely.

Industry
Computer Software, Semiconductors, Wireless

Employment Type
Full-time

Job Functions
Engineering, Information Technology

Source : LinkedIn 

Looking for 4+ Years PD/STA Engineers with Innovus Experience.
Need is immediate.
Suitable candidates, please send your CVs to: raja@chipontime.com.

Seniority Level
Associate

Industry
Semiconductors

Employment Type
Full-time

Job Functions
Engineering, Information Technology

Source: LinkedIn

About the job

– Complex SOC Top Physical Implementation for next generation SoCs by means of Synthesis , Place and Route, STA and Physical signoffs

– Hands on experience doing physical design and timing closure of complex blocks and full-chip designs

– Should have strong understanding of timing, power and area trade-offs.

– Power user of industry standard tools (ICC/Innovous/DC/Genus/PT/ETS) and able to understand their capabilities

– Solid Understanding of scripting languages such as Perl/Tcl

– Experience with large SOC designs (>20M gates) with frequencies in excess of 1GHZ .

– Familiar with deep sub-micron designs (14nm/10nm) and associated issues (manufacturability, power, signal integrity, scaling)

– Familiar with typical SoC issues such as multiple voltage and clock domains, ESD strategies, mixed signal block integration, and package interactions.

– Familiar in hierarchical design, top-down design, budgeting, timing and physical convergence

– Experience in top level floorplanning including partition shaping and sizing, pin placement, channel planning,

high speed signal and clock planning and feed-through planning in a plus

– Good understanding of Physical Design Verification methodology to debug LVS/DRC issues at chip/block level

– Should have gone through recent successful SoC tape-outs.

Seniority Level
Mid-Senior level

Industry
Consumer Electronics, Semiconductors

Employment Type
Full-time

Job Functions
Information Technology

Source: LinkedIn

Position Description:

To be part of a highly skilled and challenging high speed PHY design team working on the latest technology nodes (12nm and below).
Develop algorithms for DDR trainings, sub blocks such as data and address modules
Responsible for all aspects of design and verification from spec to silicon along with interface design for controller and SoC.
Active involvement in problem solving and implementing opportunities for improvement
Mentoring and coaching other design team members on technical issues
Pair with Analog designers to ensure smooth interface between Digital and Analog circuits
Equal opportunity position with excellent pay package!

SKILLS required:

Experience on design of DDR PHY with full ownership from specifications to silicon
Strong knowledge of DDR/LPDDR JEDEC protocol
Experience with DDR training algorithms and data path designs
Strong fundamental knowledge of Verilog and scripting languages, timing closure, DFT, Synthesis, Lint & CDC
Experience in Asynchronous domain transfer designs, APB/JTAG, DFI
The position requires good written & verbal communication skills as well a strong commitment and ability to work in cross functional and globally dispersed teams.
M.S./M.Tech, BS/BE (Electronics)
Experience Required : 4-10 Years
All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, veteran or disability status.

Seniority Level
Mid-Senior level

Industry
Computer Hardware, Electrical & Electronic Manufacturing, Semiconductors

Employment Type
Full-time

Job Functions
Engineering

Source: LinkedIn 

Job Responsibilities:

The Employee Is Expected To Take Ownership Of Full Chip/multiple Complex Design & Flow Challenges, Which Would Include

The employee is responsible for complete physical design of multiple large & complex blocks & sub-system implementation 28nm/16nm and below technology nodes.
Floor-planning, Place & Route and CTS using physical design tools
Physical verification and IP Integration
Physical Design Flow and Methodology
Ability to lead the team along with the project execution
Use metric-driven techniques to help ensure first-pass working silicon.
Communicate regularly with the implementation and project team to resolve issues, and communicate status to leads
Occasional travel needed

Job Qualifications

This position requires at least B.E/B.Tech/M.Tech in Electronics with ASIC development experience in a fast paced environment with following experience.
12+ years of relevant experience
Expertise in Physical Design activities: Floor-planning, CTS, P&R, Extraction, Power IR/EM, Physical Verification (DRC/LVS) and Signal Integrity
Static Timing/Crosstalk Analysis and timing closure
Must have an understanding of Synthesis/DFT concepts and flow
Experience in working with analog IP, hard and soft macros and delivering hierarchical design projects
Expertise with Backend Tools (Innovus or ICC, PVS, Tempus, Voltus, QRC)
Strong programming knowledge in Perl, TCL, and/or Shell and Python Scripting
Excellent oral and written communications skills in order to work with teams across the globe.

Seniority Level
Mid-Senior level

Industry
Electrical & Electronic Manufacturing, Semiconductors

Employment Type
Full-time

Job Functions
Engineering

Source: LinkedIn 

Immediate And Excellent Opportunities For M.Tech Trained (VLSI) freshers.

Skills :
– Trained or did Internship in Verification.
– Have strong knowledge in System Verilog, Digital electronics, Verilog.
– Good communication skills.
– Open for Noida Location.

Interested please share your resume on madhuri.tomar@incise.in

Nvidia is Hiring!

The teams have several job openings for Senior, New college Grad and Intern positions in Physical Design, ASIC Design, CAD Design, ASIC Verification.

Check out careers @ https://lnkd.in/gqZ8B4A and IM with specific job IDs and Resume.

All the best !! 

Roles and Responsibilities:

Intern- RTL- GDS (Physical Design)
Position Title: Intern

Work Area:RTL to GDS ( Physical design)

Location: Bangalore

Summary of Role:

Work with RTL to GDS Implementation team on the Synthesis, Place and Route and flow & automation, along with EM/IR drop Analysis along with Physical verification in various technology nodes.

Required Qualifications:

Pursuing Bachelor, Masters OR PhD degree in Electronics (Bachelors/ Master- 2021 passing out students & PhD Ongoing)

Be able to collaborate with program and technical design leads on multiple concurrent projects.

Should have excellent problem solving skills, written & oral communication, teaming & interpersonal skills

Perform all activities in a safe and responsible manner and support all Environmental, Health, Safety & Security requirements and programs

Additional Eligibility Qualifications:

Preferred Qualifications:

Should have good understanding of VLSI Design and CMOS technology

Knowledge of the end-to-end Physical design cycles

Knowledge in RTL coding process desired.

Good automation and scripting skill.

Source : Naukri

Roles and Responsibilities

Position Title: Intern
Internship position for M.S / PhD students in Memory Solutions Group, GlobalFoundries (GF) Bangalore

GlobalFoundries (GF) Bangalore is seeking a highly skilled and motivated semiconductor development engineer for an internship position. The student will work for embedded memory development in GF Bangalore. The responsibility includes design, characterization as well as documentation and verification for testing preparation and possibly silicon mask design.

Essential Responsibilities:

Circuit design, layout and analysis.
Verification (LVS/DRC)
Test and Hardware characterization
Perform all activities in a safe and responsible manner and support all Environmental, Health, Safety & Security requirements and programs
The intern/Co-Op will work directly with existing team working on embedded memory design, test, and analysis.

The intern will have the opportunity to learn about advanced semiconductor memory design

The assignment would involve getting exposure to leading edge foundry EDA tools, design flows, and yield / design interaction.

Required Qualifications:

Masters / PhD Student enrolled in an accredited program on Electrical Engineering, Computer Engineering, Computer Science, Physics, or related fields.
Minimum of 3 months experience with UNIX environment.
VLSI design courses / experience
Familiarity with CADENCE design system.
Familiarity with scripting language is preferred.
Excellent academic standing.
Strong written and oral communications skills.
Attention to detail.
Self-motivated; able to take ownership of assignments, develop work plans and proactively seek feedback to ensure objectives are aligned and met.
Team player; able to succeed in a dynamic, fast paced environment.

Source: Naukri 

Job Overview

In the wireless connectivity IP validation engineer role you are responsible to developing, executing and debug issues in connectivity IP. In this position you will be responsible for developing and executing embedded bare metal C code to validate IP design, silicon bring-up activities, characterization and optimizing of RF parameters on silicon. Knowledge of wireless systems that include radio and baseband hardware, and protocol stack software such as Bluetooth, WLAN, FM, IEEE 802.15.4 or NFC with testing experience is needed.

Day to day activities will include testing and debug of wireless connectivity HW IP and lower layer controller FW in pre-silicon emulation and post-silicon validation environment, system bring-up & integration, optimization and characterization. Responsibilities also include working with design engineers to analyze and troubleshoot problems, interpreting wireless specifications and product requirements, organizing test results, compiling and presenting test reports, and logging defects into the defect tracking system. To succeed in this position, you must possess knowledge of standard lab equipment including Oscilloscope, Logic Analyzer, Protocol analyzers, and RF test equipment.

Skills/Experience

Qualified candidates must have BSEE with 0 – 5 years of experience. Experienced with C or C++ or similar programming language and revision control tools. Familiarity with embedded FW development and computer architecture. Familiarity with Python, TCL, Pearl or similar scripting language. Knowledge or experience with the Bluetooth, FM, IEEE 802.15.4 or NFC wireless standard is a plus.

Education Requirements

Required: Bachelor’s, Electrical Engineering Preferred: Master’s, Electrical Engineering

Source: Naukri 

Job description
General Summary:

We are looking for Engineers with up to four years of experience for developer roles in the rapidly expanding QIPL WLAN micro-Code team. The job involves developing drivers in C on IU based controllers for wireless PHY layer (IEEE 802.11family) baseband hardware in Qualcomm s proprietary Wi-Fi modem solutions.

In the process you would build a deep appreciation of the full life-cycle of design, development and commercialization of the latest generation (Lithium/Beryllium) of Wi-Fi modem chips that go into Qualcomm s market leading Access Point and User Equipment solutions.

Strong C-programming/debugging skills and an understanding of wireless L1/PHY/MAC layers are necessary. A passion to understand PHY/MAC HW blocks and for developing embedded drivers to interface with them is essential. Good interpersonal communication skills and a willingness to work with multi-sited teams are strongly desired.

Source: Naukri 

Job duties and responsibilities:

As member of central physical design team, you will provide backend design service for multiple Marvell SOC design groups, from floor planning, power grid design, place and route, clock tree synthesis, timing closure, power/signal integrity analysis, to physical verification (DRC/LVS/Antenna).
You will have the opportunity to work on many varieties of challenging designs, i.e. low power and high speed SOCs.
You will work closely with frontend and integration team to ensure successful tapeouts.

Qualifications and experience required:

BE/BTech in EE/EC + 2 years or ME/MTech in EE/EC with 0-1 years of experience.
Exposure on ASIC design, layout and semiconductor device/process through previous work/intern experience or course work.
Experience with scripting/programming using Tcl/Tk/Perl.
Detail oriented, self-motivated team worker, good verbal and written communication skills.
Previous experience on physical design and automatic place and route a plus. i.e.
Knowledge of Synopsys/Cadence P&R tools.
Previous experience on custom layout and physical verification a plus.
Previous experience on synthesis/STA a plus.

Source: careersquare.in