Tag VLSI

VIAs in VLSI

What are VIAs in VLSI? To connect between different metal layers, we need poly layer along with the metal layers that we are going to connect. These are basically called as VIAs. From the below picture we can see that…

Metal Layers

What are Metal Layers? To route any PG/Clock/Signal we need metal layers. Metal layers connect the points of the two ends.   There can be many numbers of metal layers which has been used to complete the routing. The number…

Congestion

What is Congestion? If the number of required routing resources are more than the number of available routing tracks, then the area becomes congested. High congestion causes detours and leads to worse results. Congestion makes the design non-routable that means…

Placement Optimization

What is Placement Optimization? Optimization is the process of iterating through a design such that it meets timing, area and power specifications. The design must satisfy these multiple design objectives. In general, optimization can be broken down into the following…

Refine Placement & Detailed Placement

Refine Placement (Legalization) Legalization makes the rough solution from global placement legal (i.e., no placement constraint violation) by moving modules around locally. Looking at the Congestion, Timing and Power the objects are moved within the region to achieve the goal.…

Global Placement

During placement, following three stages happens: Global Placement Refine Placement (Legalization) Detailed Placement Global Placement Global placement is very first stage of the placement where cells are placed inside the core area for the first time looking at the timing…

Placement

What is Placement? Once we are done with the floorplan after placing all the physical cells inside the core boundary, we are left with standard cells which are still sitting out of the core design area. Now we need to…