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VLSI – Physical Design
VLSI Course – Experienced
VLSI Course – Freshers
Synthesis
Synthesis Overview and Inputs
Types of Synthesis
Physical Synthesis
RTL Quality Effect on Synthesis
Physical Design
Physical Design Flow
Physical Design Inputs
Physical Design Inputs
Synthesized Netlist
Design Exchange Format (DEF)
Physical Library (LEF)
Timing Library (.lib)
Standard Design Constraints (.sdc)
Unified Power Format (.upf)
Floorplan
Floorplan Overview
Macros
Macro Placement Guidelines
Floorplan Module Constraints
Blockages
Decap Cells
AON Cells
TIE Cells in VLSI
Isolation Cells
Retention Flops
Level Shifter Cells
Boundary Cap Cells/End Caps
Tap Cells
Power Switch Cells
PG Grid Insertion
Pin & Power Mux Placement
Placement
Placement Overview
Pre Placement Sanity Checks
Global Placement
Refine & Detailed Placement
Scan Chain Reordering
Placement Optimization
Congestion
Performance (Timing)
Power
Clock Tree Synthesis (CTS)
CTS Overview
CTS Spec File
Useful Skew
Duty Cycle & Pulse Width
ICG Cell & Related Concepts
Signal Integrity & Crosstalk
Routing
Routing Overview
Metal Layers
Pitch, Spacing & Offset
VIAs
Scripting
SHELL Scripting
Basic Linux Commands
GREP Commands
AWK Commands
SED Commands
GVIM Commands
TCL Scripting
Basics of TCL
Decision in TCL
LOOPS in TCL
ARRAY in TCL
String in TCL
List in TCL
Procedure in TCL
File IO in TCL
Regular Expressions in TCL
Practical Exposure to writing TCL with examples
PERL Scripting
Interview QA
Floorplan Q n A
Placement Q n A
CTS Q n A
Routing Q n A
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